133466c3bb
Currently, there are two major issues with stmmac driver statistics First of all, statistics in stmmac_extra_stats, stmmac_rxq_stats and stmmac_txq_stats are 32 bit variables on 32 bit platforms. This can cause some stats to overflow after several minutes of high traffic, for example rx_pkt_n, tx_pkt_n and so on. Secondly, if HW supports multiqueues, there are frequent cacheline ping pongs on some driver statistic vars, for example, normal_irq_n, tx_pkt_n and so on. What's more, frequent cacheline ping pongs on normal_irq_n happens in ISR, this makes the situation worse. To improve the driver, we convert those statistics to 64 bit, implement ndo_get_stats64 and update .get_ethtool_stats implementation accordingly. We also use per-queue statistics where necessary to remove the cacheline ping pongs as much as possible to make multiqueue operations faster. Those statistics which are not possible to overflow and not frequently updated are kept as is. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Link: https://lore.kernel.org/r/20230717160630.1892-3-jszhang@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
125 lines
3.7 KiB
C
125 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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This is the driver for the MAC 10/100 on-chip Ethernet controller
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currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
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DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
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this code.
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This contains the functions to handle the dma.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <asm/io.h>
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#include "dwmac100.h"
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#include "dwmac_dma.h"
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static void dwmac100_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, int atds)
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{
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/* Enable Application Access by writing to DMA CSR0 */
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writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
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ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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}
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static void dwmac100_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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dma_addr_t dma_rx_phy, u32 chan)
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{
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/* RX descriptor base addr lists must be written into DMA CSR3 */
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
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}
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static void dwmac100_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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dma_addr_t dma_tx_phy, u32 chan)
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{
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/* TX descriptor base addr lists must be written into DMA CSR4 */
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
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}
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/* Store and Forward capability is not used at all.
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*
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* The transmit threshold can be programmed by setting the TTC bits in the DMA
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* control register.
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*/
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static void dwmac100_dma_operation_mode_tx(struct stmmac_priv *priv,
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void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (mode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (mode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else
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csr6 |= DMA_CONTROL_TTC_128;
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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static void dwmac100_dump_dma_regs(struct stmmac_priv *priv,
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void __iomem *ioaddr, u32 *reg_space)
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{
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int i;
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for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++)
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reg_space[DMA_BUS_MODE / 4 + i] =
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readl(ioaddr + DMA_BUS_MODE + i * 4);
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reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
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readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
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reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
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readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
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}
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/* DMA controller has two counters to track the number of the missed frames. */
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static void dwmac100_dma_diagnostic_fr(struct stmmac_extra_stats *x,
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void __iomem *ioaddr)
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{
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u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
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if (unlikely(csr8)) {
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if (csr8 & DMA_MISSED_FRAME_OVE) {
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x->rx_overflow_cntr += 0x800;
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} else {
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unsigned int ove_cntr;
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ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
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x->rx_overflow_cntr += ove_cntr;
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}
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if (csr8 & DMA_MISSED_FRAME_OVE_M) {
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x->rx_missed_cntr += 0xffff;
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} else {
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unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
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x->rx_missed_cntr += miss_f;
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}
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}
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}
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const struct stmmac_dma_ops dwmac100_dma_ops = {
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.reset = dwmac_dma_reset,
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.init = dwmac100_dma_init,
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.init_rx_chan = dwmac100_dma_init_rx,
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.init_tx_chan = dwmac100_dma_init_tx,
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.dump_regs = dwmac100_dump_dma_regs,
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.dma_tx_mode = dwmac100_dma_operation_mode_tx,
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.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
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.enable_dma_transmission = dwmac_enable_dma_transmission,
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.enable_dma_irq = dwmac_enable_dma_irq,
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.disable_dma_irq = dwmac_disable_dma_irq,
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.start_tx = dwmac_dma_start_tx,
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.stop_tx = dwmac_dma_stop_tx,
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.start_rx = dwmac_dma_start_rx,
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.stop_rx = dwmac_dma_stop_rx,
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.dma_interrupt = dwmac_dma_interrupt,
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};
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