e8f9392a5c
In order to use minimum of hard coded values common to LKD and F/W a dynamic method to work with PLLs is introduced in this patch. Formerly asic specific PLL numbering is now common for all asics. To be backward compatible a bit in dev status is defined, if the bit is not set LKD will keep working with old PLL numbering. Signed-off-by: Ohad Sharabi <osharabi@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
21 lines
413 B
C
21 lines
413 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GOYA_FW_IF_H
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#define GOYA_FW_IF_H
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#define GOYA_EVENT_QUEUE_MSIX_IDX 5
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#define CPU_BOOT_ADDR 0x7FF8040000ull
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#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */
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#define LINUX_FW_OFFSET 0x800000 /* 8MB in DDR */
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#define GOYA_PLL_FREQ_LOW 50000000 /* 50 MHz */
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#endif /* GOYA_FW_IF_H */
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