linux

iv/linux

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Gabriel Fernandez 46a57afdd7 drivers: clk: st: PLL rate change implementation for DVFS

Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

2015-10-08 23:52:58 -07:00

clk-flexgen.c

clk: st: fix handling result of of_property_count_strings

2015-10-01 15:21:50 -07:00

clkgen-fsyn.c

drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

2015-09-17 11:51:43 -07:00

clkgen-mux.c

drivers: clk: st: PLL rate change implementation for DVFS

2015-10-08 23:52:58 -07:00

clkgen-pll.c

drivers: clk: st: PLL rate change implementation for DVFS