Adrian Hunter 46f4a69ec8 mmc: sdhci: Add LTR support for some Intel BYT based controllers
Some Intel BYT based host controllers support the setting of latency
tolerance.  Accordingly, implement the PM QoS ->set_latency_tolerance()
callback.  The raw register values are also exposed via debugfs.

Intel EHL controllers require this support.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: cb3a7d4a0aec4e ("mmc: sdhci-pci: Add support for Intel EHL")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200818104508.7149-1-adrian.hunter@intel.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-07 09:11:29 +02:00
..
2020-03-24 14:39:52 +01:00
2020-05-28 11:22:15 +02:00
2020-05-28 11:22:14 +02:00
2020-08-05 13:23:24 -07:00
2019-07-11 18:11:21 -07:00