47169fba3a
More cases of code insertion via macros that does not add a great deal. All the additions have to be specified in the macro arguments, so they can just as well go after the macro. No generated code change. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
707 lines
20 KiB
C
707 lines
20 KiB
C
#ifndef _ASM_POWERPC_EXCEPTION_H
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#define _ASM_POWERPC_EXCEPTION_H
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/*
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* Extracted from head_64.S
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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*
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* This file contains the low-level support and setup for the
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* PowerPC-64 platform, including trap and interrupt dispatch.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/*
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* The following macros define the code that appears as
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* the prologue to each of the exception handlers. They
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* are split into two parts to allow a single kernel binary
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* to be used for pSeries and iSeries.
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*
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* We make as much of the exception code common between native
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* exception handlers (including pSeries LPAR) and iSeries LPAR
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* implementations as possible.
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*/
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#include <asm/head-64.h>
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#include <asm/feature-fixups.h>
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/* PACA save area offsets (exgen, exmc, etc) */
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#define EX_R9 0
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#define EX_R10 8
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#define EX_R11 16
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#define EX_R12 24
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#define EX_R13 32
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#define EX_DAR 40
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#define EX_DSISR 48
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#define EX_CCR 52
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#define EX_CFAR 56
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#define EX_PPR 64
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#if defined(CONFIG_RELOCATABLE)
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#define EX_CTR 72
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#define EX_SIZE 10 /* size in u64 units */
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#else
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#define EX_SIZE 9 /* size in u64 units */
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#endif
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/*
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* maximum recursive depth of MCE exceptions
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*/
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#define MAX_MCE_DEPTH 4
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/*
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* EX_R3 is only used by the bad_stack handler. bad_stack reloads and
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* saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap
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* with EX_DAR.
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*/
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#define EX_R3 EX_DAR
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#ifdef __ASSEMBLY__
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#define STF_ENTRY_BARRIER_SLOT \
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STF_ENTRY_BARRIER_FIXUP_SECTION; \
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nop; \
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nop; \
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nop
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#define STF_EXIT_BARRIER_SLOT \
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STF_EXIT_BARRIER_FIXUP_SECTION; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop
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/*
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* r10 must be free to use, r13 must be paca
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*/
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#define INTERRUPT_TO_KERNEL \
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STF_ENTRY_BARRIER_SLOT
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/*
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* Macros for annotating the expected destination of (h)rfid
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*
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* The nop instructions allow us to insert one or more instructions to flush the
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* L1-D cache when returning to userspace or a guest.
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*/
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#define RFI_FLUSH_SLOT \
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RFI_FLUSH_FIXUP_SECTION; \
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nop; \
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nop; \
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nop
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#define RFI_TO_KERNEL \
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rfid
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#define RFI_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define RFI_TO_USER_OR_KERNEL \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define RFI_TO_GUEST \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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rfid; \
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b rfi_flush_fallback
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#define HRFI_TO_KERNEL \
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hrfid
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#define HRFI_TO_USER \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_USER_OR_KERNEL \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_GUEST \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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#define HRFI_TO_UNKNOWN \
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STF_EXIT_BARRIER_SLOT; \
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RFI_FLUSH_SLOT; \
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hrfid; \
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b hrfi_flush_fallback
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/*
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* We're short on space and time in the exception prolog, so we can't
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* use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
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* Instead we get the base of the kernel from paca->kernelbase and or in the low
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* part of label. This requires that the label be within 64KB of kernelbase, and
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* that kernelbase be 64K aligned.
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*/
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#define LOAD_HANDLER(reg, label) \
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ld reg,PACAKBASE(r13); /* get high part of &label */ \
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ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
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#define __LOAD_HANDLER(reg, label) \
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ld reg,PACAKBASE(r13); \
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ori reg,reg,(ABS_ADDR(label))@l
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/*
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* Branches from unrelocated code (e.g., interrupts) to labels outside
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* head-y require >64K offsets.
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*/
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#define __LOAD_FAR_HANDLER(reg, label) \
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ld reg,PACAKBASE(r13); \
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ori reg,reg,(ABS_ADDR(label))@l; \
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addis reg,reg,(ABS_ADDR(label))@h
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.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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.if ! \set_ri
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xori r10,r10,MSR_RI /* Clear MSR_RI */
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.endif
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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.if \hsrr
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mtspr SPRN_HSRR0,r12
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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HRFI_TO_KERNEL
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.else
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mtspr SPRN_SRR0,r12
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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RFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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.endm
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.macro EXCEPTION_PROLOG_2_VIRT label, hsrr
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#ifdef CONFIG_RELOCATABLE
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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mtctr r12
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.if \hsrr
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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bctr
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#else
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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b \label
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#endif
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.endm
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/*
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* As EXCEPTION_PROLOG(), except we've already got relocation on so no need to
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* rfid. Save CTR in case we're CONFIG_RELOCATABLE, in which case
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* EXCEPTION_PROLOG_2_VIRT will be using CTR.
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*/
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#define EXCEPTION_RELON_PROLOG(area, label, hsrr, kvm, vec) \
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SET_SCRATCH0(r13); /* save r13 */ \
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EXCEPTION_PROLOG_0 area ; \
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EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \
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EXCEPTION_PROLOG_2_VIRT label, hsrr
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/* Exception register prefixes */
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#define EXC_HV 1
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#define EXC_STD 0
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#if defined(CONFIG_RELOCATABLE)
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/*
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* If we support interrupts with relocation on AND we're a relocatable kernel,
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* we need to use CTR to get to the 2nd level handler. So, save/restore it
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* when required.
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*/
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#define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
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#define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
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#define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
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#else
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/* ...else CTR is unused and in register. */
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#define SAVE_CTR(reg, area)
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#define GET_CTR(reg, area) mfctr reg
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#define RESTORE_CTR(reg, area)
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#endif
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/*
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* PPR save/restore macros used in exceptions_64s.S
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* Used for P7 or later processors
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*/
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#define SAVE_PPR(area, ra) \
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BEGIN_FTR_SECTION_NESTED(940) \
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ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \
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std ra,_PPR(r1); \
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END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
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#define RESTORE_PPR_PACA(area, ra) \
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BEGIN_FTR_SECTION_NESTED(941) \
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ld ra,area+EX_PPR(r13); \
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mtspr SPRN_PPR,ra; \
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END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
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/*
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* Get an SPR into a register if the CPU has the given feature
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*/
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#define OPT_GET_SPR(ra, spr, ftr) \
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BEGIN_FTR_SECTION_NESTED(943) \
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mfspr ra,spr; \
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END_FTR_SECTION_NESTED(ftr,ftr,943)
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/*
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* Set an SPR from a register if the CPU has the given feature
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*/
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#define OPT_SET_SPR(ra, spr, ftr) \
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BEGIN_FTR_SECTION_NESTED(943) \
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mtspr spr,ra; \
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END_FTR_SECTION_NESTED(ftr,ftr,943)
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/*
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* Save a register to the PACA if the CPU has the given feature
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*/
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#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
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BEGIN_FTR_SECTION_NESTED(943) \
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std ra,offset(r13); \
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END_FTR_SECTION_NESTED(ftr,ftr,943)
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.macro EXCEPTION_PROLOG_0 area
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GET_PACA(r13)
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std r9,\area\()+EX_R9(r13) /* save r9 */
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OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
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HMT_MEDIUM
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std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
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OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
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.endm
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.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
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OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
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INTERRUPT_TO_KERNEL
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SAVE_CTR(r10, \area\())
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mfcr r9
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.if \kvm
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KVMTEST \hsrr \vec
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.endif
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.if \bitmask
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lbz r10,PACAIRQSOFTMASK(r13)
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andi. r10,r10,\bitmask
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/* Associate vector numbers with bits in paca->irq_happened */
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.if \vec == 0x500 || \vec == 0xea0
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li r10,PACA_IRQ_EE
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.elseif \vec == 0x900
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li r10,PACA_IRQ_DEC
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.elseif \vec == 0xa00 || \vec == 0xe80
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li r10,PACA_IRQ_DBELL
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.elseif \vec == 0xe60
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li r10,PACA_IRQ_HMI
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.elseif \vec == 0xf00
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li r10,PACA_IRQ_PMI
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.else
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.abort "Bad maskable vector"
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.endif
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.if \hsrr
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bne masked_Hinterrupt
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.else
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bne masked_interrupt
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.endif
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.endif
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std r11,\area\()+EX_R11(r13)
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std r12,\area\()+EX_R12(r13)
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GET_SCRATCH0(r10)
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std r10,\area\()+EX_R13(r13)
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.endm
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#define EXCEPTION_PROLOG(area, label, hsrr, kvm, vec) \
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SET_SCRATCH0(r13); /* save r13 */ \
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EXCEPTION_PROLOG_0 area ; \
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EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \
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EXCEPTION_PROLOG_2_REAL label, hsrr, 1
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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* If hv is possible, interrupts come into to the hv version
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* of the kvmppc_interrupt code, which then jumps to the PR handler,
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* kvmppc_interrupt_pr, if the guest is a PR guest.
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*/
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#define kvmppc_interrupt kvmppc_interrupt_hv
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#else
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#define kvmppc_interrupt kvmppc_interrupt_pr
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#endif
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/*
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* Branch to label using its 0xC000 address. This results in instruction
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* address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
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* on using mtmsr rather than rfid.
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*
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* This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
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* load KBASE for a slight optimisation.
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*/
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#define BRANCH_TO_C000(reg, label) \
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__LOAD_HANDLER(reg, label); \
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mtctr reg; \
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bctr
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#ifdef CONFIG_RELOCATABLE
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#define BRANCH_TO_COMMON(reg, label) \
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__LOAD_HANDLER(reg, label); \
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mtctr reg; \
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bctr
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#define BRANCH_LINK_TO_FAR(label) \
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__LOAD_FAR_HANDLER(r12, label); \
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mtctr r12; \
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bctrl
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/*
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* KVM requires __LOAD_FAR_HANDLER.
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*
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* __BRANCH_TO_KVM_EXIT branches are also a special case because they
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* explicitly use r9 then reload it from PACA before branching. Hence
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* the double-underscore.
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*/
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#define __BRANCH_TO_KVM_EXIT(area, label) \
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mfctr r9; \
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std r9,HSTATE_SCRATCH1(r13); \
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__LOAD_FAR_HANDLER(r9, label); \
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mtctr r9; \
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ld r9,area+EX_R9(r13); \
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bctr
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#else
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#define BRANCH_TO_COMMON(reg, label) \
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b label
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#define BRANCH_LINK_TO_FAR(label) \
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bl label
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#define __BRANCH_TO_KVM_EXIT(area, label) \
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ld r9,area+EX_R9(r13); \
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b label
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#endif
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/* Do not enable RI */
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#define EXCEPTION_PROLOG_NORI(area, label, hsrr, kvm, vec) \
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EXCEPTION_PROLOG_0 area ; \
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EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \
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EXCEPTION_PROLOG_2_REAL label, hsrr, 0
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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.macro KVMTEST hsrr, n
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lbz r10,HSTATE_IN_GUEST(r13)
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cmpwi r10,0
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.if \hsrr
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bne do_kvm_H\n
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.else
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bne do_kvm_\n
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.endif
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.endm
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.macro KVM_HANDLER area, hsrr, n, skip
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.if \skip
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cmpwi r10,KVM_GUEST_MODE_SKIP
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beq 89f
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.else
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BEGIN_FTR_SECTION_NESTED(947)
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ld r10,\area+EX_CFAR(r13)
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std r10,HSTATE_CFAR(r13)
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END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
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.endif
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BEGIN_FTR_SECTION_NESTED(948)
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ld r10,\area+EX_PPR(r13)
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std r10,HSTATE_PPR(r13)
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END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
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ld r10,\area+EX_R10(r13)
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std r12,HSTATE_SCRATCH0(r13)
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sldi r12,r9,32
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/* HSRR variants have the 0x2 bit added to their trap number */
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.if \hsrr
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ori r12,r12,(\n + 0x2)
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.else
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ori r12,r12,(\n)
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.endif
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/* This reloads r9 before branching to kvmppc_interrupt */
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__BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt)
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.if \skip
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89: mtocrf 0x80,r9
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ld r9,\area+EX_R9(r13)
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ld r10,\area+EX_R10(r13)
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.if \hsrr
|
|
b kvmppc_skip_Hinterrupt
|
|
.else
|
|
b kvmppc_skip_interrupt
|
|
.endif
|
|
.endif
|
|
.endm
|
|
|
|
#else
|
|
.macro KVMTEST hsrr, n
|
|
.endm
|
|
.macro KVM_HANDLER area, hsrr, n, skip
|
|
.endm
|
|
#endif
|
|
|
|
#define EXCEPTION_PROLOG_COMMON_1() \
|
|
std r9,_CCR(r1); /* save CR in stackframe */ \
|
|
std r11,_NIP(r1); /* save SRR0 in stackframe */ \
|
|
std r12,_MSR(r1); /* save SRR1 in stackframe */ \
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|
std r10,0(r1); /* make stack chain pointer */ \
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|
std r0,GPR0(r1); /* save r0 in stackframe */ \
|
|
std r10,GPR1(r1); /* save r1 in stackframe */ \
|
|
|
|
|
|
/*
|
|
* The common exception prolog is used for all except a few exceptions
|
|
* such as a segment miss on a kernel address. We have to be prepared
|
|
* to take another exception from the point where we first touch the
|
|
* kernel stack onwards.
|
|
*
|
|
* On entry r13 points to the paca, r9-r13 are saved in the paca,
|
|
* r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
|
|
* SRR1, and relocation is on.
|
|
*/
|
|
#define EXCEPTION_PROLOG_COMMON(n, area) \
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|
andi. r10,r12,MSR_PR; /* See if coming from user */ \
|
|
mr r10,r1; /* Save r1 */ \
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|
subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
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|
beq- 1f; \
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|
ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
|
|
1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
|
|
blt+ cr1,3f; /* abort if it is */ \
|
|
li r1,(n); /* will be reloaded later */ \
|
|
sth r1,PACA_TRAP_SAVE(r13); \
|
|
std r3,area+EX_R3(r13); \
|
|
addi r3,r13,area; /* r3 -> where regs are saved*/ \
|
|
RESTORE_CTR(r1, area); \
|
|
b bad_stack; \
|
|
3: EXCEPTION_PROLOG_COMMON_1(); \
|
|
kuap_save_amr_and_lock r9, r10, cr1, cr0; \
|
|
beq 4f; /* if from kernel mode */ \
|
|
ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
|
|
SAVE_PPR(area, r9); \
|
|
4: EXCEPTION_PROLOG_COMMON_2(area) \
|
|
EXCEPTION_PROLOG_COMMON_3(n) \
|
|
ACCOUNT_STOLEN_TIME
|
|
|
|
/* Save original regs values from save area to stack frame. */
|
|
#define EXCEPTION_PROLOG_COMMON_2(area) \
|
|
ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
|
|
ld r10,area+EX_R10(r13); \
|
|
std r9,GPR9(r1); \
|
|
std r10,GPR10(r1); \
|
|
ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
|
|
ld r10,area+EX_R12(r13); \
|
|
ld r11,area+EX_R13(r13); \
|
|
std r9,GPR11(r1); \
|
|
std r10,GPR12(r1); \
|
|
std r11,GPR13(r1); \
|
|
BEGIN_FTR_SECTION_NESTED(66); \
|
|
ld r10,area+EX_CFAR(r13); \
|
|
std r10,ORIG_GPR3(r1); \
|
|
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
|
|
GET_CTR(r10, area); \
|
|
std r10,_CTR(r1);
|
|
|
|
#define EXCEPTION_PROLOG_COMMON_3(n) \
|
|
std r2,GPR2(r1); /* save r2 in stackframe */ \
|
|
SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
|
|
SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
|
|
mflr r9; /* Get LR, later save to stack */ \
|
|
ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
|
|
std r9,_LINK(r1); \
|
|
lbz r10,PACAIRQSOFTMASK(r13); \
|
|
mfspr r11,SPRN_XER; /* save XER in stackframe */ \
|
|
std r10,SOFTE(r1); \
|
|
std r11,_XER(r1); \
|
|
li r9,(n)+1; \
|
|
std r9,_TRAP(r1); /* set trap number */ \
|
|
li r10,0; \
|
|
ld r11,exception_marker@toc(r2); \
|
|
std r10,RESULT(r1); /* clear regs->result */ \
|
|
std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
|
|
|
|
/*
|
|
* Exception vectors.
|
|
*/
|
|
#define STD_EXCEPTION(vec, label) \
|
|
EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_STD, 1, vec);
|
|
|
|
/* Version of above for when we have to branch out-of-line */
|
|
#define __OOL_EXCEPTION(vec, label, hdlr) \
|
|
SET_SCRATCH0(r13); \
|
|
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
|
|
b hdlr
|
|
|
|
#define STD_EXCEPTION_OOL(vec, label) \
|
|
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \
|
|
EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
|
|
|
|
#define STD_EXCEPTION_HV(loc, vec, label) \
|
|
EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, 1, vec)
|
|
|
|
#define STD_EXCEPTION_HV_OOL(vec, label) \
|
|
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \
|
|
EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1
|
|
|
|
#define STD_RELON_EXCEPTION(loc, vec, label) \
|
|
/* No guest interrupts come through here */ \
|
|
EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, 0, vec)
|
|
|
|
#define STD_RELON_EXCEPTION_OOL(vec, label) \
|
|
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \
|
|
EXCEPTION_PROLOG_2_VIRT label, EXC_STD
|
|
|
|
#define STD_RELON_EXCEPTION_HV(loc, vec, label) \
|
|
EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, 1, vec)
|
|
|
|
#define STD_RELON_EXCEPTION_HV_OOL(vec, label) \
|
|
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \
|
|
EXCEPTION_PROLOG_2_VIRT label, EXC_HV
|
|
|
|
#define __MASKABLE_EXCEPTION(vec, label, hsrr, kvm, bitmask) \
|
|
SET_SCRATCH0(r13); /* save r13 */ \
|
|
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
|
|
EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \
|
|
EXCEPTION_PROLOG_2_REAL label, hsrr, 1
|
|
|
|
#define MASKABLE_EXCEPTION(vec, label, bitmask) \
|
|
__MASKABLE_EXCEPTION(vec, label, EXC_STD, 1, bitmask)
|
|
|
|
#define MASKABLE_EXCEPTION_OOL(vec, label, bitmask) \
|
|
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \
|
|
EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
|
|
|
|
#define MASKABLE_EXCEPTION_HV(vec, label, bitmask) \
|
|
__MASKABLE_EXCEPTION(vec, label, EXC_HV, 1, bitmask)
|
|
|
|
#define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \
|
|
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
|
|
EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1
|
|
|
|
#define __MASKABLE_RELON_EXCEPTION(vec, label, hsrr, kvm, bitmask) \
|
|
SET_SCRATCH0(r13); /* save r13 */ \
|
|
EXCEPTION_PROLOG_0 PACA_EXGEN ; \
|
|
EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \
|
|
EXCEPTION_PROLOG_2_VIRT label, hsrr
|
|
|
|
#define MASKABLE_RELON_EXCEPTION(vec, label, bitmask) \
|
|
__MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, 0, bitmask)
|
|
|
|
#define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask) \
|
|
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, bitmask ; \
|
|
EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
|
|
|
|
#define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask) \
|
|
__MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, 1, bitmask)
|
|
|
|
#define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \
|
|
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
|
|
EXCEPTION_PROLOG_2_VIRT label, EXC_HV
|
|
|
|
#define RUNLATCH_ON \
|
|
BEGIN_FTR_SECTION \
|
|
ld r3, PACA_THREAD_INFO(r13); \
|
|
ld r4,TI_LOCAL_FLAGS(r3); \
|
|
andi. r0,r4,_TLF_RUNLATCH; \
|
|
beql ppc64_runlatch_on_trampoline; \
|
|
END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
|
|
|
|
#define EXCEPTION_COMMON(area, trap) \
|
|
EXCEPTION_PROLOG_COMMON(trap, area); \
|
|
|
|
/*
|
|
* Exception where stack is already set in r1, r1 is saved in r10
|
|
*/
|
|
#define EXCEPTION_COMMON_STACK(area, trap) \
|
|
EXCEPTION_PROLOG_COMMON_1(); \
|
|
kuap_save_amr_and_lock r9, r10, cr1; \
|
|
EXCEPTION_PROLOG_COMMON_2(area); \
|
|
EXCEPTION_PROLOG_COMMON_3(trap)
|
|
|
|
#define STD_EXCEPTION_COMMON(trap, hdlr) \
|
|
EXCEPTION_COMMON(PACA_EXGEN, trap); \
|
|
bl save_nvgprs; \
|
|
RECONCILE_IRQ_STATE(r10, r11); \
|
|
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
|
bl hdlr; \
|
|
b ret_from_except
|
|
|
|
/*
|
|
* Like STD_EXCEPTION_COMMON, but for exceptions that can occur
|
|
* in the idle task and therefore need the special idle handling
|
|
* (finish nap and runlatch)
|
|
*/
|
|
#define STD_EXCEPTION_COMMON_ASYNC(trap, hdlr) \
|
|
EXCEPTION_COMMON(PACA_EXGEN, trap); \
|
|
FINISH_NAP; \
|
|
RECONCILE_IRQ_STATE(r10, r11); \
|
|
RUNLATCH_ON; \
|
|
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
|
bl hdlr; \
|
|
b ret_from_except_lite
|
|
|
|
/*
|
|
* When the idle code in power4_idle puts the CPU into NAP mode,
|
|
* it has to do so in a loop, and relies on the external interrupt
|
|
* and decrementer interrupt entry code to get it out of the loop.
|
|
* It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
|
|
* to signal that it is in the loop and needs help to get out.
|
|
*/
|
|
#ifdef CONFIG_PPC_970_NAP
|
|
#define FINISH_NAP \
|
|
BEGIN_FTR_SECTION \
|
|
ld r11, PACA_THREAD_INFO(r13); \
|
|
ld r9,TI_LOCAL_FLAGS(r11); \
|
|
andi. r10,r9,_TLF_NAPPING; \
|
|
bnel power4_fixup_nap; \
|
|
END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
|
|
#else
|
|
#define FINISH_NAP
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* _ASM_POWERPC_EXCEPTION_H */
|