Liu Shixin 47513f243b

riscv: Enable KFENCE for riscv64 ...

Add architecture specific implementation details for KFENCE and enable
KFENCE for the riscv64 architecture. In particular, this implements the
required interface in <asm/kfence.h>.

KFENCE requires that attributes for pages from its memory pool can
individually be set. Therefore, force the kfence pool to be mapped at
page granularity.

Testing this patch using the testcases in kfence_test.c and all passed.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Acked-by: Marco Elver <elver@google.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

2021-06-30 20:55:41 -07:00

..

boot

RISC-V Patches for the 5.13 Merge Window, Part 1

2021-05-06 09:24:18 -07:00

configs

RISC-V: Enable Microchip PolarFire ICICLE SoC

2021-04-26 08:31:32 -07:00

errata

riscv: sifive: Apply errata "cip-1200" patch

2021-04-26 08:24:58 -07:00

include

riscv: Enable KFENCE for riscv64

2021-06-30 20:55:41 -07:00

kernel

riscv: Only initialize swiotlb when necessary

2021-06-11 13:42:26 -07:00

lib

riscv: Add support for function error injection

2021-01-14 15:09:09 -08:00

mm

riscv: Enable KFENCE for riscv64

2021-06-30 20:55:41 -07:00

net

riscv: bpf: Avoid breaking W^X

2021-04-26 08:25:14 -07:00

Kbuild

riscv: Allow device trees to be built into the kernel

2020-05-18 11:38:05 -07:00

Kconfig

riscv: Enable KFENCE for riscv64

2021-06-30 20:55:41 -07:00

Kconfig.debug

RISC-V: Remove EARLY_PRINTK support

2018-12-17 10:23:46 -08:00

Kconfig.erratas

riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y

2021-05-06 09:40:13 -07:00

Kconfig.socs

RISC-V Patches for the 5.13 Merge Window, Part 1

2021-05-06 09:24:18 -07:00

Makefile

RISC-V: enable XIP

2021-04-26 08:31:28 -07:00