4763c0894a
- Fix glitch risks in the Intel GPIO - Fix the Intel Cherryview valid irq mask calculation. - Allocate the Intel Cherryview irqchip dynamically. - Fix the valid mask init sequency on the ST STMFX driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl3HVugACgkQQRCzN7AZ XXNcOw//UAEO6DnTc4+fr46Al4hsgShxlHk0URPEkMWZI7t+R6bs9icGGDOoejWS n7/Fpd7ChpYqtsRQD4sc1/hJwXxoUJFX0xzP7dI/PmT+st0OULAHjokoqK3RtERe 1shwAQq1NosIlwmsy+ZOqQwXUfq6RAnnVPblt6+VeG7Sc9bNHnDcg7d58GVFl7C3 S6D2v59pPMAL9JU+hQDQ8DiODXLk2k9k7Vtoq8bYLei0PMKdt/7I1kJjELPfghiA PMLmtTztygB27fUiFVVGVcCtaivLXqtI83yi9uYnY2rQ4Oa+zxuuej5rUL+TwybK P+XKJDNUeg/l6+wdkQXN8rJXkEXcU+Sms0HZmaYkML4l/6Oh4JtjDhij1KPqNjhY ufO7mnf2zkfooLD8rv9YC50yYKX3vZT4b5SrPnvd4lG2/C3hiZozwmAXdYtLgoqS BU9c2kfzIKHiFgBCJCnkyDesaGCfbkw5rDh1R4tSpABbShS242EdAYL0ZCuzjEsc 9iR4Jbi03mhCINjkFDbx5PnAZk8cJUeSmKFeWxDuZoUh3gU0VoPHlH533k6FsnLG Kck2sBPhpPRl/b/64jF21UDI1g3W0gxQet+hGCSYzcA/QQ0fo5+VKpGyTSvxzDnl LcbccAELH3qdzMDajtyEXaIeOv8huG9iBzS0pUibLbAsPqqrMhk= =fkcG -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - Fix glitch risks in the Intel GPIO - Fix the Intel Cherryview valid irq mask calculation. - Allocate the Intel Cherryview irqchip dynamically. - Fix the valid mask init sequency on the ST STMFX driver. * tag 'pinctrl-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: stmfx: fix valid_mask init sequence pinctrl: cherryview: Allocate IRQ chip dynamic pinctrl: cherryview: Fix irq_valid_mask calculation pinctrl: intel: Avoid potential glitches if pin is in GPIO mode