Sakari Ailus 482e75e7b3 media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
The external clock frequency times the PLL multiplier may exceed the value
range of 32-bit unsigned integers. Instead perform the same calculation y
using two divisions.

The result has some potential to be different, but that's ok: this number
is used to limit the range of pre-PLL divisors to find optimal values. So
the effect of the rare case of a different result here would mean an
invalid pre-PLL divisor is tried. That will be found out a little later in
any case.

Also guard against dividing by zero if the external clock frequency is
higher than the maximum OP PLL output clock --- a rather improbable case.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07 15:49:32 +01:00
2020-10-13 13:04:41 -07:00
2020-11-29 10:18:53 -08:00
2020-11-27 10:38:36 -08:00
2020-11-27 11:13:39 -08:00
2020-11-28 10:42:30 -08:00
2020-11-14 12:04:02 -08:00
2020-11-19 19:56:29 +01:00
2020-10-17 11:18:18 -07:00
2020-11-27 11:04:13 -08:00
2020-11-13 13:16:27 +01:00
2020-11-29 15:50:50 -08:00

Linux kernel
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