a76eb4297f
There's another kind of situation where we could potentially race with nonblocking modesets and MST, especially if we were to only use the locking provided by atomic modesetting: * Display 1 begins as enabled on DP-1 in SST mode * Display 1 switches to MST mode, exposes one sink in MST mode * Userspace does non-blocking modeset to disable the SST display * Userspace does non-blocking modeset to enable the MST display with a different CRTC, but the SST display hasn't been fully taken down yet * Execution order between the last two commits isn't guaranteed since they share no drm resources We can fix this however, by ensuring that we always pull in the atomic topology state whenever a connector capable of driving an MST display performs its atomic check - and then tracking CRTC commits happening on the SST connector in the MST topology state. So, let's add some simple helpers for doing that and hook them up in various drivers. v2: * Use intel_dp_mst_source_support() to check for MST support in i915, fixes CI failures Signed-off-by: Lyude Paul <lyude@redhat.com> Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Sean Paul <sean@poorly.run> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220817193847.557945-14-lyude@redhat.com
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
#ifndef __NV50_KMS_H__
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#define __NV50_KMS_H__
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#include <linux/workqueue.h>
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#include <nvif/mem.h>
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#include <nvif/push.h>
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#include "nouveau_display.h"
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struct nv50_msto;
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struct nouveau_encoder;
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struct nv50_disp {
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struct nvif_disp *disp;
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struct nv50_core *core;
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struct nvif_object caps;
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#define NV50_DISP_SYNC(c, o) ((c) * 0x040 + (o))
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#define NV50_DISP_CORE_NTFY NV50_DISP_SYNC(0 , 0x00)
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#define NV50_DISP_WNDW_SEM0(c) NV50_DISP_SYNC(1 + (c), 0x00)
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#define NV50_DISP_WNDW_SEM1(c) NV50_DISP_SYNC(1 + (c), 0x10)
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#define NV50_DISP_WNDW_NTFY(c) NV50_DISP_SYNC(1 + (c), 0x20)
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#define NV50_DISP_BASE_SEM0(c) NV50_DISP_WNDW_SEM0(0 + (c))
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#define NV50_DISP_BASE_SEM1(c) NV50_DISP_WNDW_SEM1(0 + (c))
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#define NV50_DISP_BASE_NTFY(c) NV50_DISP_WNDW_NTFY(0 + (c))
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#define NV50_DISP_OVLY_SEM0(c) NV50_DISP_WNDW_SEM0(4 + (c))
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#define NV50_DISP_OVLY_SEM1(c) NV50_DISP_WNDW_SEM1(4 + (c))
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#define NV50_DISP_OVLY_NTFY(c) NV50_DISP_WNDW_NTFY(4 + (c))
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struct nouveau_bo *sync;
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struct mutex mutex;
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};
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static inline struct nv50_disp *
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nv50_disp(struct drm_device *dev)
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{
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return nouveau_display(dev)->priv;
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}
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struct nv50_disp_interlock {
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enum nv50_disp_interlock_type {
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NV50_DISP_INTERLOCK_CORE = 0,
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NV50_DISP_INTERLOCK_CURS,
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NV50_DISP_INTERLOCK_BASE,
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NV50_DISP_INTERLOCK_OVLY,
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NV50_DISP_INTERLOCK_WNDW,
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NV50_DISP_INTERLOCK_WIMM,
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NV50_DISP_INTERLOCK__SIZE
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} type;
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u32 data;
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u32 wimm;
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};
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void corec37d_ntfy_init(struct nouveau_bo *, u32);
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void head907d_olut_load(struct drm_color_lut *, int size, void __iomem *);
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struct nv50_chan {
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struct nvif_object user;
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struct nvif_device *device;
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};
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struct nv50_dmac {
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struct nv50_chan base;
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struct nvif_push _push;
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struct nvif_push *push;
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u32 *ptr;
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struct nvif_object sync;
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struct nvif_object vram;
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/* Protects against concurrent pushbuf access to this channel, lock is
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* grabbed by evo_wait (if the pushbuf reservation is successful) and
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* dropped again by evo_kick. */
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struct mutex lock;
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u32 cur;
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u32 put;
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u32 max;
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};
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struct nv50_outp_atom {
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struct list_head head;
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struct drm_encoder *encoder;
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bool flush_disable;
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union nv50_outp_atom_mask {
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struct {
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bool ctrl:1;
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};
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u8 mask;
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} set, clr;
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};
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int nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
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const s32 *oclass, u8 head, void *data, u32 size,
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s64 syncbuf, struct nv50_dmac *dmac);
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void nv50_dmac_destroy(struct nv50_dmac *);
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/*
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* For normal encoders this just returns the encoder. For active MST encoders,
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* this returns the real outp that's driving displays on the topology.
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* Inactive MST encoders return NULL, since they would have no real outp to
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* return anyway.
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*/
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struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder);
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bool nv50_has_mst(struct nouveau_drm *drm);
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u32 *evo_wait(struct nv50_dmac *, int nr);
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void evo_kick(u32 *, struct nv50_dmac *);
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extern const u64 disp50xx_modifiers[];
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extern const u64 disp90xx_modifiers[];
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extern const u64 wndwc57e_modifiers[];
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#endif
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