6a08083f29
Disable PMU support when running on AMD and perf reports fewer than four general purpose counters. All AMD PMUs must define at least four counters due to AMD's legacy architecture hardcoding the number of counters without providing a way to enumerate the number of counters to software, e.g. from AMD's APM: The legacy architecture defines four performance counters (PerfCtrn) and corresponding event-select registers (PerfEvtSeln). Virtualizing fewer than four counters can lead to guest instability as software expects four counters to be available. Rather than bleed AMD details into the common code, just define a const unsigned int and provide a convenient location to document why Intel and AMD have different mins (in particular, AMD's lack of any way to enumerate less than four counters to the guest). Keep the minimum number of counters at Intel at one, even though old P6 and Core Solo/Duo processor effectively require a minimum of two counters. KVM can, and more importantly has up until this point, supported a vPMU so long as the CPU has at least one counter. Perf's support for P6/Core CPUs does require two counters, but perf will happily chug along with a single counter when running on a modern CPU. Cc: Jim Mattson <jmattson@google.com> Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Like Xu <likexu@tencent.com> [sean: set Intel min to '1', not '2'] Link: https://lore.kernel.org/r/20230603011058.1038821-8-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com> |
||
|---|---|---|
| .. | ||
| capabilities.h | ||
| hyperv.c | ||
| hyperv.h | ||
| nested.c | ||
| nested.h | ||
| pmu_intel.c | ||
| posted_intr.c | ||
| posted_intr.h | ||
| run_flags.h | ||
| sgx.c | ||
| sgx.h | ||
| vmcs12.c | ||
| vmcs12.h | ||
| vmcs_shadow_fields.h | ||
| vmcs.h | ||
| vmenter.S | ||
| vmx_ops.h | ||
| vmx.c | ||
| vmx.h | ||