3aefb2ee5b
This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. [Palmer: Some minor fixups, including a RISCV_ISA_ZICBOM dependency on MMU that's probably not strictly necessary. The Zicbom support will trip up sparse for users that have new toolchains, I just sent a patch.] Link: https://lore.kernel.org/all/20220706231536.2041855-1-heiko@sntech.de/ Link: https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/T/#u * palmer/riscv-zicbom: riscv: implement cache-management errata for T-Head SoCs riscv: Add support for non-coherent devices using zicbom extension dt-bindings: riscv: document cbom-block-size of: also handle dma-noncoherent in of_dma_is_coherent()
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* RISC-V specific functions to support DMA for non-coherent devices
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*/
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#include <linux/dma-direct.h>
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#include <linux/dma-map-ops.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <asm/cacheflush.h>
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static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
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static bool noncoherent_supported;
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_TO_DEVICE:
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ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
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break;
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case DMA_FROM_DEVICE:
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ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
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break;
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case DMA_BIDIRECTIONAL:
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ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
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break;
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default:
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break;
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}
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}
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_TO_DEVICE:
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break;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
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break;
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default:
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break;
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}
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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void *flush_addr = page_address(page);
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ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
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}
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void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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const struct iommu_ops *iommu, bool coherent)
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{
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WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN,
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TAINT_CPU_OUT_OF_SPEC,
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"%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)",
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dev_driver_string(dev), dev_name(dev),
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ARCH_DMA_MINALIGN, riscv_cbom_block_size);
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WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC,
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"%s %s: device non-coherent but no non-coherent operations supported",
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dev_driver_string(dev), dev_name(dev));
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dev->dma_coherent = coherent;
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}
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#ifdef CONFIG_RISCV_ISA_ZICBOM
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void riscv_init_cbom_blocksize(void)
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{
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struct device_node *node;
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int ret;
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u32 val;
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for_each_of_cpu_node(node) {
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unsigned long hartid;
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int cbom_hartid;
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ret = riscv_of_processor_hartid(node, &hartid);
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if (ret)
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continue;
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if (hartid < 0)
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continue;
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/* set block-size for cbom extension if available */
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ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
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if (ret)
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continue;
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if (!riscv_cbom_block_size) {
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riscv_cbom_block_size = val;
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cbom_hartid = hartid;
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} else {
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if (riscv_cbom_block_size != val)
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pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
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cbom_hartid, hartid);
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}
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}
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}
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#endif
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void riscv_noncoherent_supported(void)
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{
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noncoherent_supported = true;
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}
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