b3a9801ccc
X86 defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. - PIC Mode: Legacy external 8259 compliant PIC interrupt controller - Virtual Wire Mode: Use lapic as virtual wire interrupt delivery mode ACPI and MPS spec compliant systems provide this information, but for OF based systems, it is by default set to PIC mode. In fact it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for the lapic interrupt controller node which allows to configure it for virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221124084143.21841-3-rtanwar@maxlinear.com
72 lines
2.3 KiB
YAML
72 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
|
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|
|
|
title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
|
|
|
|
maintainers:
|
|
- Rahul Tanwar <rtanwar@maxlinear.com>
|
|
|
|
description: |
|
|
Intel's Advanced Programmable Interrupt Controller (APIC) is a
|
|
family of interrupt controllers. The APIC is a split
|
|
architecture design, with a local component (LAPIC) integrated
|
|
into the processor itself and an external I/O APIC. Local APIC
|
|
(lapic) receives interrupts from the processor's interrupt pins,
|
|
from internal sources and from an external I/O APIC (ioapic).
|
|
And it sends these to the processor core for handling.
|
|
See [1] Chapter 8 for more details.
|
|
|
|
Many of the Intel's generic devices like hpet, ioapic, lapic have
|
|
the ce4100 name in their compatible property names because they
|
|
first appeared in CE4100 SoC.
|
|
|
|
This schema defines bindings for local APIC interrupt controller.
|
|
|
|
[1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
|
|
|
|
properties:
|
|
compatible:
|
|
const: intel,ce4100-lapic
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupt-controller: true
|
|
|
|
'#interrupt-cells':
|
|
const: 2
|
|
|
|
intel,virtual-wire-mode:
|
|
description: Intel defines a few possible interrupt delivery
|
|
modes. With respect to boot/init time, mainly two interrupt
|
|
delivery modes are possible.
|
|
PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
|
|
Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
|
|
For ACPI or MPS spec compliant systems, it is figured out by some read
|
|
only bit field/s available in their respective defined data structures.
|
|
For OF based systems, it is by default set to PIC mode.
|
|
But if this optional boolean property is set, then the interrupt delivery
|
|
mode is configured to virtual wire compatibility mode.
|
|
type: boolean
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupt-controller
|
|
- '#interrupt-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
lapic0: interrupt-controller@fee00000 {
|
|
compatible = "intel,ce4100-lapic";
|
|
reg = <0xfee00000 0x1000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
intel,virtual-wire-mode;
|
|
};
|