linux/Documentation/devicetree/bindings/riscv
Palmer Dabbelt 6710e07f01
Merge patch series "riscv,isa fixups"
Conor Dooley <conor@kernel.org> says:

From: Conor Dooley <conor.dooley@microchip.com>

I noticed ~today~ while looking at the isa manual that I had not
accounted for another couple of edge cases with my regex. As before, I
think attempting to validate the canonical order for multiletter stuff
makes no sense - but we should totally try to avoid false-positives for
combinations that are known to be valid.

* b4-shazam-merge:
  dt-bindings: riscv: fix single letter canonical order
  dt-bindings: riscv: fix underscore requirement for multi-letter extensions

Link: https://lore.kernel.org/r/20221205174459.60195-1-conor@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-01-06 10:31:12 -08:00
..
canaan.yaml dt-bindings: add Canaan boards compatible strings 2021-02-22 17:51:06 -08:00
cpus.yaml Merge patch series "riscv,isa fixups" 2023-01-06 10:31:12 -08:00
microchip.yaml RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00
sifive,ccache0.yaml dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache 2022-10-13 11:06:50 -07:00
sifive.yaml dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board 2021-01-07 17:37:41 -08:00
starfive.yaml dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board 2022-11-04 11:37:06 +00:00