060f03e954
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
175 lines
5.0 KiB
C
175 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
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*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
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#include "../core.h"
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#include "../pinconf.h"
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#include "../pinmux.h"
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#include "pinctrl-starfive-jh7110.h"
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#define JH7110_AON_NGPIO 4
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#define JH7110_AON_GC_BASE 64
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/* registers */
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#define JH7110_AON_DOEN 0x0
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#define JH7110_AON_DOUT 0x4
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#define JH7110_AON_GPI 0x8
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#define JH7110_AON_GPIOIN 0x2c
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#define JH7110_AON_GPIOEN 0xc
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#define JH7110_AON_GPIOIS 0x10
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#define JH7110_AON_GPIOIC 0x14
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#define JH7110_AON_GPIOIBE 0x18
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#define JH7110_AON_GPIOIEV 0x1c
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#define JH7110_AON_GPIOIE 0x20
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#define JH7110_AON_GPIORIS 0x28
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#define JH7110_AON_GPIOMIS 0x28
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#define JH7110_AON_GPO_PDA_0_5_CFG 0x30
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static const struct pinctrl_pin_desc jh7110_aon_pins[] = {
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PINCTRL_PIN(PAD_TESTEN, "TESTEN"),
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PINCTRL_PIN(PAD_RGPIO0, "RGPIO0"),
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PINCTRL_PIN(PAD_RGPIO1, "RGPIO1"),
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PINCTRL_PIN(PAD_RGPIO2, "RGPIO2"),
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PINCTRL_PIN(PAD_RGPIO3, "RGPIO3"),
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PINCTRL_PIN(PAD_RSTN, "RSTN"),
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PINCTRL_PIN(PAD_GMAC0_MDC, "GMAC0_MDC"),
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PINCTRL_PIN(PAD_GMAC0_MDIO, "GMAC0_MDIO"),
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PINCTRL_PIN(PAD_GMAC0_RXD0, "GMAC0_RXD0"),
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PINCTRL_PIN(PAD_GMAC0_RXD1, "GMAC0_RXD1"),
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PINCTRL_PIN(PAD_GMAC0_RXD2, "GMAC0_RXD2"),
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PINCTRL_PIN(PAD_GMAC0_RXD3, "GMAC0_RXD3"),
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PINCTRL_PIN(PAD_GMAC0_RXDV, "GMAC0_RXDV"),
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PINCTRL_PIN(PAD_GMAC0_RXC, "GMAC0_RXC"),
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PINCTRL_PIN(PAD_GMAC0_TXD0, "GMAC0_TXD0"),
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PINCTRL_PIN(PAD_GMAC0_TXD1, "GMAC0_TXD1"),
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PINCTRL_PIN(PAD_GMAC0_TXD2, "GMAC0_TXD2"),
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PINCTRL_PIN(PAD_GMAC0_TXD3, "GMAC0_TXD3"),
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PINCTRL_PIN(PAD_GMAC0_TXEN, "GMAC0_TXEN"),
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PINCTRL_PIN(PAD_GMAC0_TXC, "GMAC0_TXC"),
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};
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static int jh7110_aon_set_one_pin_mux(struct jh7110_pinctrl *sfp,
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unsigned int pin,
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unsigned int din, u32 dout,
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u32 doen, u32 func)
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{
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if (pin < sfp->gc.ngpio && func == 0)
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jh7110_set_gpiomux(sfp, pin, din, dout, doen);
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return 0;
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}
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static int jh7110_aon_get_padcfg_base(struct jh7110_pinctrl *sfp,
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unsigned int pin)
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{
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if (pin < PAD_GMAC0_MDC)
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return JH7110_AON_GPO_PDA_0_5_CFG;
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return -1;
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}
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static void jh7110_aon_irq_handler(struct irq_desc *desc)
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{
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struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long mis;
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unsigned int pin;
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chained_irq_enter(chip, desc);
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mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS);
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for_each_set_bit(pin, &mis, JH7110_AON_NGPIO)
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generic_handle_domain_irq(sfp->gc.irq.domain, pin);
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chained_irq_exit(chip, desc);
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}
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static int jh7110_aon_init_hw(struct gpio_chip *gc)
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{
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struct jh7110_pinctrl *sfp = container_of(gc,
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struct jh7110_pinctrl, gc);
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/* mask all GPIO interrupts */
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writel_relaxed(0, sfp->base + JH7110_AON_GPIOIE);
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/* clear edge interrupt flags */
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writel_relaxed(0, sfp->base + JH7110_AON_GPIOIC);
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writel_relaxed(0x0f, sfp->base + JH7110_AON_GPIOIC);
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/* enable GPIO interrupts */
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writel_relaxed(1, sfp->base + JH7110_AON_GPIOEN);
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return 0;
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}
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static const struct jh7110_gpio_irq_reg jh7110_aon_irq_reg = {
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.is_reg_base = JH7110_AON_GPIOIS,
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.ic_reg_base = JH7110_AON_GPIOIC,
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.ibe_reg_base = JH7110_AON_GPIOIBE,
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.iev_reg_base = JH7110_AON_GPIOIEV,
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.ie_reg_base = JH7110_AON_GPIOIE,
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.ris_reg_base = JH7110_AON_GPIORIS,
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.mis_reg_base = JH7110_AON_GPIOMIS,
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};
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static const struct jh7110_pinctrl_soc_info jh7110_aon_pinctrl_info = {
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.pins = jh7110_aon_pins,
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.npins = ARRAY_SIZE(jh7110_aon_pins),
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.ngpios = JH7110_AON_NGPIO,
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.gc_base = JH7110_AON_GC_BASE,
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.dout_reg_base = JH7110_AON_DOUT,
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.dout_mask = GENMASK(3, 0),
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.doen_reg_base = JH7110_AON_DOEN,
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.doen_mask = GENMASK(2, 0),
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.gpi_reg_base = JH7110_AON_GPI,
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.gpi_mask = GENMASK(3, 0),
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.gpioin_reg_base = JH7110_AON_GPIOIN,
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.irq_reg = &jh7110_aon_irq_reg,
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.jh7110_set_one_pin_mux = jh7110_aon_set_one_pin_mux,
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.jh7110_get_padcfg_base = jh7110_aon_get_padcfg_base,
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.jh7110_gpio_irq_handler = jh7110_aon_irq_handler,
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.jh7110_gpio_init_hw = jh7110_aon_init_hw,
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};
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static const struct of_device_id jh7110_aon_pinctrl_of_match[] = {
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{
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.compatible = "starfive,jh7110-aon-pinctrl",
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.data = &jh7110_aon_pinctrl_info,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7110_aon_pinctrl_of_match);
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static struct platform_driver jh7110_aon_pinctrl_driver = {
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.probe = jh7110_pinctrl_probe,
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.driver = {
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.name = "starfive-jh7110-aon-pinctrl",
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.of_match_table = jh7110_aon_pinctrl_of_match,
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},
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};
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module_platform_driver(jh7110_aon_pinctrl_driver);
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MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller");
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MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
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MODULE_LICENSE("GPL");
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