The current msi_ops are short sighted in a number of ways, this patch attempts to fix the glaring deficiences. - Report in msi_ops if a 64bit address is needed in the msi message, so we can fail 32bit only msi structures. - Send and receive a full struct msi_msg in both setup and target. This is a little cleaner and allows for architectures that need to modify the data to retarget the msi interrupt to a different cpu. - In target pass in the full cpu mask instead of just the first cpu in case we can make use of the full cpu mask. - Operate in terms of irqs and not vectors, currently there is still a 1-1 relationship but on architectures other than ia64 I expect this will change. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rajesh Shah <rajesh.shah@intel.com> Cc: Andi Kleen <ak@muc.de> Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
212 lines
5.1 KiB
C
212 lines
5.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/cpumask.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/nodepda.h>
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#include "msi.h"
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struct sn_msi_info {
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u64 pci_addr;
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struct sn_irq_info *sn_irq_info;
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};
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static struct sn_msi_info *sn_msi_info;
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static void
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sn_msi_teardown(unsigned int irq)
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{
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nasid_t nasid;
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int widget;
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struct pci_dev *pdev;
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struct pcidev_info *sn_pdev;
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struct sn_irq_info *sn_irq_info;
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struct pcibus_bussoft *bussoft;
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struct sn_pcibus_provider *provider;
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sn_irq_info = sn_msi_info[irq].sn_irq_info;
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if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
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return;
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sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
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pdev = sn_pdev->pdi_linux_pcidev;
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provider = SN_PCIDEV_BUSPROVIDER(pdev);
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(*provider->dma_unmap)(pdev,
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sn_msi_info[irq].pci_addr,
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PCI_DMA_FROMDEVICE);
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sn_msi_info[irq].pci_addr = 0;
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bussoft = SN_PCIDEV_BUSSOFT(pdev);
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nasid = NASID_GET(bussoft->bs_base);
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widget = (nasid & 1) ?
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TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
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SWIN_WIDGETNUM(bussoft->bs_base);
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sn_intr_free(nasid, widget, sn_irq_info);
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sn_msi_info[irq].sn_irq_info = NULL;
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return;
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}
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int
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sn_msi_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
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{
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int widget;
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int status;
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nasid_t nasid;
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u64 bus_addr;
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struct sn_irq_info *sn_irq_info;
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struct pcibus_bussoft *bussoft = SN_PCIDEV_BUSSOFT(pdev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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if (bussoft == NULL)
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return -EINVAL;
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if (provider == NULL || provider->dma_map_consistent == NULL)
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return -EINVAL;
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/*
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* Set up the vector plumbing. Let the prom (via sn_intr_alloc)
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* decide which cpu to direct this msi at by default.
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*/
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nasid = NASID_GET(bussoft->bs_base);
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widget = (nasid & 1) ?
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TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
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SWIN_WIDGETNUM(bussoft->bs_base);
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sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
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if (! sn_irq_info)
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return -ENOMEM;
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status = sn_intr_alloc(nasid, widget, sn_irq_info, irq, -1, -1);
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if (status) {
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kfree(sn_irq_info);
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return -ENOMEM;
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}
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sn_irq_info->irq_int_bit = -1; /* mark this as an MSI irq */
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sn_irq_fixup(pdev, sn_irq_info);
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/* Prom probably should fill these in, but doesn't ... */
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sn_irq_info->irq_bridge_type = bussoft->bs_asic_type;
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sn_irq_info->irq_bridge = (void *)bussoft->bs_base;
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/*
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* Map the xio address into bus space
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*/
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bus_addr = (*provider->dma_map_consistent)(pdev,
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sn_irq_info->irq_xtalkaddr,
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sizeof(sn_irq_info->irq_xtalkaddr),
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SN_DMA_MSI|SN_DMA_ADDR_XIO);
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if (! bus_addr) {
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sn_intr_free(nasid, widget, sn_irq_info);
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kfree(sn_irq_info);
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return -ENOMEM;
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}
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sn_msi_info[irq].sn_irq_info = sn_irq_info;
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sn_msi_info[irq].pci_addr = bus_addr;
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msg->address_hi = (u32)(bus_addr >> 32);
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msg->address_lo = (u32)(bus_addr & 0x00000000ffffffff);
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/*
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* In the SN platform, bit 16 is a "send vector" bit which
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* must be present in order to move the vector through the system.
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*/
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msg->data = 0x100 + irq;
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#ifdef CONFIG_SMP
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set_irq_affinity_info(irq, sn_irq_info->irq_cpuid, 0);
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#endif
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return 0;
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}
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static void
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sn_msi_target(unsigned int irq, cpumask_t cpu_mask, struct msi_msg *msg)
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{
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int slice;
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nasid_t nasid;
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u64 bus_addr;
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struct pci_dev *pdev;
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struct pcidev_info *sn_pdev;
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struct sn_irq_info *sn_irq_info;
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struct sn_irq_info *new_irq_info;
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struct sn_pcibus_provider *provider;
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unsigned int cpu;
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cpu = first_cpu(cpu_mask);
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sn_irq_info = sn_msi_info[irq].sn_irq_info;
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if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
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return;
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/*
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* Release XIO resources for the old MSI PCI address
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*/
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sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
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pdev = sn_pdev->pdi_linux_pcidev;
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provider = SN_PCIDEV_BUSPROVIDER(pdev);
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bus_addr = (u64)(msg->address_hi) << 32 | (u64)(msg->address_lo);
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(*provider->dma_unmap)(pdev, bus_addr, PCI_DMA_FROMDEVICE);
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sn_msi_info[irq].pci_addr = 0;
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nasid = cpuid_to_nasid(cpu);
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slice = cpuid_to_slice(cpu);
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new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice);
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sn_msi_info[irq].sn_irq_info = new_irq_info;
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if (new_irq_info == NULL)
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return;
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/*
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* Map the xio address into bus space
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*/
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bus_addr = (*provider->dma_map_consistent)(pdev,
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new_irq_info->irq_xtalkaddr,
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sizeof(new_irq_info->irq_xtalkaddr),
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SN_DMA_MSI|SN_DMA_ADDR_XIO);
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sn_msi_info[irq].pci_addr = bus_addr;
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msg->address_hi = (u32)(bus_addr >> 32);
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msg->address_lo = (u32)(bus_addr & 0x00000000ffffffff);
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}
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struct msi_ops sn_msi_ops = {
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.needs_64bit_address = 1,
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.setup = sn_msi_setup,
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.teardown = sn_msi_teardown,
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#ifdef CONFIG_SMP
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.target = sn_msi_target,
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#endif
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};
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int
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sn_msi_init(void)
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{
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sn_msi_info =
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kzalloc(sizeof(struct sn_msi_info) * NR_IRQS, GFP_KERNEL);
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if (! sn_msi_info)
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return -ENOMEM;
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msi_register(&sn_msi_ops);
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return 0;
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}
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