0829edc43e
When processing data read the full fifo data in 1 time. If there are several samples in the FIFO, it means we are experiencing system delay. In this case, it is better to read all data with 1 bus access than to add additional latency by doing several ones. This requires to use a bigger buffer depending on chip FIFO size and do an additional local data copy before sending. But the cost is minimal and behavior is still better like this under system heavy load. Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com> Link: https://lore.kernel.org/r/20230623082924.283967-1-inv.git-commit@tdk.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> |
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| .. | ||
| inv_mpu_acpi.c | ||
| inv_mpu_aux.c | ||
| inv_mpu_aux.h | ||
| inv_mpu_core.c | ||
| inv_mpu_i2c.c | ||
| inv_mpu_iio.h | ||
| inv_mpu_magn.c | ||
| inv_mpu_magn.h | ||
| inv_mpu_ring.c | ||
| inv_mpu_spi.c | ||
| inv_mpu_trigger.c | ||
| Kconfig | ||
| Makefile | ||