Paul Walmsley 4c8eb19cf9 riscv: tlbflush: remove confusing comment on local_flush_tlb_all() ... Remove a confusing comment on our local_flush_tlb_all() implementation. Per an internal discussion with Andrew, while it's true that the fence.i is not necessary, it's not the case that an sfence.vma implies a fence.i. We also drop the section about "flush[ing] the entire local TLB" to better align with the language in section 4.2.1 "Supervisor Memory-Management Fence Instruction" of the RISC-V Privileged Specification v20190608. Fixes: c901e45a99 ("RISC-V: `sfence.vma` orderes the instruction cache") Reported-by: Alan Kao <alankao@andestech.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Andrew Waterman <andrew@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-10-14 12:35:36 -07:00
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asm	riscv: tlbflush: remove confusing comment on local_flush_tlb_all()	2019-10-14 12:35:36 -07:00
uapi/asm	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00