6c247393cf
Add registers, bit fields and compatible strings for Exynos7 TMU
(Thermal Management Unit). Following are a few of the differences
in the Exynos7 TMU from earlier SoCs:
- 8 trigger levels
- Different bit offsets and more registers for the rising
and falling thresholds.
- New power down detection bit in the TMU_CONTROL register
which does not update the CURRENT_TEMP0 when tmu power down
is detected.
- Change in bit offset for the NEXT_DATA field of EMUL_CON
register. EMUL_CON register address has also changed.
- INTSTAT and INTCLEAR registers present in earlier SoCs
have been combined into one INTPEND register. The register
address for INTCLEAR and INTPEND is also different.
- Since there are 8 rising/falling interrupts as against
at most 4 in earlier SoCs the INTEN bit offsets are different.
- Multiple probe support which is handled by a TMU_CONTROL1
register (No support for this in the current patch).
This patch adds special clock support required only for Exynos7. It
also updates the "code_to_temp" prototype as Exynos7 has 9 bit
code-temp mapping.
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/*
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* exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
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*
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* Copyright (C) 2011 Samsung Electronics
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* Donggeun Kim <dg77.kim@samsung.com>
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _EXYNOS_TMU_H
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#define _EXYNOS_TMU_H
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#include <linux/cpu_cooling.h>
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#include <dt-bindings/thermal/thermal_exynos.h>
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enum soc_type {
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SOC_ARCH_EXYNOS3250 = 1,
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SOC_ARCH_EXYNOS4210,
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SOC_ARCH_EXYNOS4412,
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SOC_ARCH_EXYNOS5250,
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SOC_ARCH_EXYNOS5260,
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SOC_ARCH_EXYNOS5420,
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SOC_ARCH_EXYNOS5420_TRIMINFO,
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SOC_ARCH_EXYNOS5440,
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SOC_ARCH_EXYNOS7,
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};
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/**
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* struct exynos_tmu_platform_data
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* @gain: gain of amplifier in the positive-TC generator block
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* 0 < gain <= 15
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* @reference_voltage: reference voltage of amplifier
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* in the positive-TC generator block
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* 0 < reference_voltage <= 31
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* @noise_cancel_mode: noise cancellation mode
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* 000, 100, 101, 110 and 111 can be different modes
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* @type: determines the type of SOC
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* @efuse_value: platform defined fuse value
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* @min_efuse_value: minimum valid trimming data
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* @max_efuse_value: maximum valid trimming data
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* @default_temp_offset: default temperature offset in case of no trimming
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* @cal_type: calibration type for temperature
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*
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* This structure is required for configuration of exynos_tmu driver.
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*/
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struct exynos_tmu_platform_data {
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u8 gain;
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u8 reference_voltage;
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u8 noise_cancel_mode;
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u32 efuse_value;
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u32 min_efuse_value;
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u32 max_efuse_value;
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u8 first_point_trim;
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u8 second_point_trim;
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u8 default_temp_offset;
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enum soc_type type;
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u32 cal_type;
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u32 cal_mode;
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};
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#endif /* _EXYNOS_TMU_H */
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