cf4881c129
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3
DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE
module clock).
Fix this by change the clock descriptions to use the clocks of H3.
Fixes: 763c5bd045 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
313 lines
8.1 KiB
C
313 lines
8.1 KiB
C
/*
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* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "ccu_common.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_reset.h"
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#include "ccu-sun8i-de2.h"
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static SUNXI_CCU_GATE(bus_mixer0_clk, "bus-mixer0", "bus-de",
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0x04, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de",
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0x04, BIT(1), 0);
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static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de",
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0x04, BIT(2), 0);
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static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div",
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0x00, BIT(0), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div",
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0x00, BIT(1), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
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0x00, BIT(2), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
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CLK_SET_RATE_PARENT);
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static struct ccu_common *sun8i_a83t_de2_clks[] = {
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&mixer0_clk.common,
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&mixer1_clk.common,
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&wb_clk.common,
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&bus_mixer0_clk.common,
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&bus_mixer1_clk.common,
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&bus_wb_clk.common,
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&mixer0_div_a83_clk.common,
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&mixer1_div_a83_clk.common,
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&wb_div_a83_clk.common,
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};
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static struct ccu_common *sun8i_h3_de2_clks[] = {
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&mixer0_clk.common,
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&mixer1_clk.common,
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&wb_clk.common,
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&bus_mixer0_clk.common,
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&bus_mixer1_clk.common,
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&bus_wb_clk.common,
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&mixer0_div_clk.common,
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&mixer1_div_clk.common,
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&wb_div_clk.common,
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};
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static struct ccu_common *sun8i_v3s_de2_clks[] = {
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&mixer0_clk.common,
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&wb_clk.common,
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&bus_mixer0_clk.common,
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&bus_wb_clk.common,
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&mixer0_div_clk.common,
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&wb_div_clk.common,
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};
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static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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[CLK_MIXER1] = &mixer1_clk.common.hw,
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[CLK_WB] = &wb_clk.common.hw,
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[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
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[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
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[CLK_BUS_WB] = &bus_wb_clk.common.hw,
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[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
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[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
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[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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[CLK_MIXER1] = &mixer1_clk.common.hw,
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[CLK_WB] = &wb_clk.common.hw,
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[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
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[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
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[CLK_BUS_WB] = &bus_wb_clk.common.hw,
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[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
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[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
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[CLK_WB_DIV] = &wb_div_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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[CLK_WB] = &wb_clk.common.hw,
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[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
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[CLK_BUS_WB] = &bus_wb_clk.common.hw,
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[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
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[CLK_WB_DIV] = &wb_div_clk.common.hw,
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},
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.num = CLK_NUMBER,
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};
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static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
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[RST_MIXER0] = { 0x08, BIT(0) },
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/*
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* For A83T, H3 and R40, mixer1 reset line is shared with wb, so
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* only RST_WB is exported here.
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* For V3s there's just no mixer1, so it also shares this struct.
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*/
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[RST_WB] = { 0x08, BIT(2) },
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};
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static struct ccu_reset_map sun50i_a64_de2_resets[] = {
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[RST_MIXER0] = { 0x08, BIT(0) },
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[RST_MIXER1] = { 0x08, BIT(1) },
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[RST_WB] = { 0x08, BIT(2) },
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};
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static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
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.ccu_clks = sun8i_a83t_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
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.hw_clks = &sun8i_a83t_de2_hw_clks,
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.resets = sun8i_a83t_de2_resets,
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
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.ccu_clks = sun8i_h3_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun8i_a83t_de2_resets,
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
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.ccu_clks = sun8i_h3_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun50i_a64_de2_resets,
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.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
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};
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static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
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.ccu_clks = sun8i_v3s_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
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.hw_clks = &sun8i_v3s_de2_hw_clks,
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.resets = sun8i_a83t_de2_resets,
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static int sunxi_de2_clk_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct clk *bus_clk, *mod_clk;
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struct reset_control *rstc;
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void __iomem *reg;
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const struct sunxi_ccu_desc *ccu_desc;
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int ret;
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ccu_desc = of_device_get_match_data(&pdev->dev);
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if (!ccu_desc)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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bus_clk = devm_clk_get(&pdev->dev, "bus");
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if (IS_ERR(bus_clk)) {
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ret = PTR_ERR(bus_clk);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
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return ret;
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}
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mod_clk = devm_clk_get(&pdev->dev, "mod");
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if (IS_ERR(mod_clk)) {
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ret = PTR_ERR(mod_clk);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret);
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return ret;
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}
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rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(rstc)) {
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ret = PTR_ERR(rstc);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev,
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"Couldn't get reset control: %d\n", ret);
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return ret;
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}
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/* The clocks need to be enabled for us to access the registers */
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ret = clk_prepare_enable(bus_clk);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(mod_clk);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret);
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goto err_disable_bus_clk;
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}
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/* The reset control needs to be asserted for the controls to work */
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ret = reset_control_deassert(rstc);
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if (ret) {
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dev_err(&pdev->dev,
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"Couldn't deassert reset control: %d\n", ret);
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goto err_disable_mod_clk;
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}
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ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc);
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if (ret)
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goto err_assert_reset;
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return 0;
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err_assert_reset:
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reset_control_assert(rstc);
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err_disable_mod_clk:
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clk_disable_unprepare(mod_clk);
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err_disable_bus_clk:
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clk_disable_unprepare(bus_clk);
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return ret;
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}
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static const struct of_device_id sunxi_de2_clk_ids[] = {
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{
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.compatible = "allwinner,sun8i-a83t-de2-clk",
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.data = &sun8i_a83t_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun8i-h3-de2-clk",
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.data = &sun8i_h3_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun8i-v3s-de2-clk",
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.data = &sun8i_v3s_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun50i-h5-de2-clk",
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.data = &sun50i_a64_de2_clk_desc,
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},
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/*
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* The Allwinner A64 SoC needs some bit to be poke in syscon to make
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* DE2 really working.
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* So there's currently no A64 compatible here.
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* H5 shares the same reset line with A64, so here H5 is using the
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* clock description of A64.
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*/
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{ }
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};
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static struct platform_driver sunxi_de2_clk_driver = {
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.probe = sunxi_de2_clk_probe,
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.driver = {
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.name = "sunxi-de2-clks",
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.of_match_table = sunxi_de2_clk_ids,
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},
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};
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builtin_platform_driver(sunxi_de2_clk_driver);
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