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* Several patches fixing up incorrectly defined register addresses and
bitfield offsets that could lead to undefined operation when accessing
respective registers or bitfields.
1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
2a) clk: samsung: exynos5250: Fix ACP gate register offset
2b) clk: samsung: exynos5250: Add MDMA0 clocks
2c) ARM: dts: exynos5250: Fix MDMA0 clock number
3) clk: samsung: exynos4: Correct SRC_MFC register
All three issues have been present since Exynos5250 and Exynos4 clock
drivers were added by commits 6e3ad26816 ("clk: exynos5250:
register clocks using common clock framework") and e062b57177
("clk: exynos4: register clocks using common clock framework")
respectively.
* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
cause undefined operation of several peripherals, such as USB, I2C,
MIPI or display block.
4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
clock
Present since Exynos5250 clock drivers was added by commits
6e3ad26816 ("clk: exynos5250: register clocks using common clock
framework").
* Patch fixing compilation warning in clk-exynos-audss driver when
CONFIG_PM_SLEEP is disabled.
5) clk: exynos: File scope reg_save array should depend on PM_SLEEP
Present since the driver was added by commit 1241ef94cc ("clk:
samsung: register audio subsystem clocks using common clock
framework").
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJSxY6TAAoJEIv3Hb8G/XruUcgP/001H5qqDZWtEk2Z1XvOUPgF
MfFprrNcPpLhLmBnvDpR5mUrcMIp4t/4GcWClmX58zcsZfcQP5YF81oGGiQy+U13
Yu94H+sWihrms5h8GSkqEhB5YSvcIOfs4rtAeNl/g2su7i+l4loF/xofXpj09+qp
xnmKJ8yfB5RD822StgrkoMu7vxzYyK05j8IasSH54vsO9X3Z3jTWuAKdQFKZoZp4
xBGjtIwoyyHndWAlhl1nIj1dvaDgx+gF25qRUrfShfE51R4BNzmvpgiN1mpQTjCl
JpYDJqZ1h7FL883ZXiz7SfRVv4H2GaEWqz+zxgVfHkO45lIL3Eyn1zhSKas4pRFH
KZscKBvT/YEgIQjBW4+VdMuMM0NWIzvYp1BM2/l88KvUgXYiS0EOM5UjYJatKwIO
MW4ZLpIsMiJlN8OygBTaZOZQaY8rbbdVn5KFsgkL0zl7uZzmbYCqhxKrXZfTKyx/
ieEGRmqjrcuguVDPNSsd9TZ/LUm3kTCSzpr3gvAXjK+29DbVrs6fX1lQ0RCxvACQ
8gBjD6ZsVFcsGSbWbPEoDi+qtKielZBjbSrgTDNkRqE/6yqg+UUZVSJJ6kkEA14o
swE+8mGrUhdv5TvpTjJactnBZeUpFbmLm4TE/r695dfwcr6wX7cK41gMVo7bE9fk
2rYzz35ed29q8OfJI/54
=0B0x
-----END PGP SIGNATURE-----
Merge tag 'samsung-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes
Samsung Clock fixes for 3.13-rc7
* Several patches fixing up incorrectly defined register addresses and
bitfield offsets that could lead to undefined operation when accessing
respective registers or bitfields.
1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
2a) clk: samsung: exynos5250: Fix ACP gate register offset
2b) clk: samsung: exynos5250: Add MDMA0 clocks
2c) ARM: dts: exynos5250: Fix MDMA0 clock number
3) clk: samsung: exynos4: Correct SRC_MFC register
All three issues have been present since Exynos5250 and Exynos4 clock
drivers were added by commits 6e3ad26816 ("clk: exynos5250:
register clocks using common clock framework") and e062b57177
("clk: exynos4: register clocks using common clock framework")
respectively.
* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
cause undefined operation of several peripherals, such as USB, I2C,
MIPI or display block.
4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
clock
Present since Exynos5250 clock drivers was added by commits
6e3ad26816 ("clk: exynos5250: register clocks using common clock
framework").
* Patch fixing compilation warning in clk-exynos-audss driver when
CONFIG_PM_SLEEP is disabled.
5) clk: exynos: File scope reg_save array should depend on PM_SLEEP
Present since the driver was added by commit 1241ef94cc ("clk:
samsung: register audio subsystem clocks using common clock
framework").
497d2214e5
