3367934dd3
The Devicetree bindings document does not have to say in the title that it is a "Devicetree binding" or a "schema", but instead just describe the hardware. Manual updates to various binding titles, including capitalizing them. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # opp Link: https://lore.kernel.org/r/20221216163815.522628-10-krzysztof.kozlowski@linaro.org [robh: add trivial-devices.yaml and net/can/microchip,mcp251xfd.yaml] Signed-off-by: Rob Herring <robh@kernel.org>
98 lines
2.5 KiB
YAML
98 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SC8280XP
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains for the two MDSS instances on SC8280XP.
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See also:
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include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-dispcc0
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- qcom,sc8280xp-dispcc1
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clocks:
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items:
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- description: AHB interface clock,
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- description: SoC CXO clock
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- description: SoC sleep clock
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- description: DisplayPort 0 link clock
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- description: DisplayPort 0 VCO div clock
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- description: DisplayPort 1 link clock
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- description: DisplayPort 1 VCO div clock
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- description: DisplayPort 2 link clock
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- description: DisplayPort 2 VCO div clock
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- description: DisplayPort 3 link clock
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- description: DisplayPort 3 VCO div clock
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- description: DSI 0 PLL byte clock
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- description: DSI 0 PLL DSI clock
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- description: DSI 1 PLL byte clock
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- description: DSI 1 PLL DSI clock
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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power-domains:
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items:
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- description: MMCX power domain
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sc8280xp-dispcc0";
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reg = <0x0af00000 0x20000>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&mdss0_dp_phy0 0>,
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<&mdss0_dp_phy0 1>,
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<&mdss0_dp_phy1 0>,
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<&mdss0_dp_phy1 1>,
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<&mdss0_dp_phy2 0>,
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<&mdss0_dp_phy2 1>,
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<&mdss0_dp_phy3 0>,
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<&mdss0_dp_phy3 1>,
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<&mdss0_dsi0_phy 0>,
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<&mdss0_dsi0_phy 1>,
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<&mdss0_dsi1_phy 0>,
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<&mdss0_dsi1_phy 1>;
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power-domains = <&rpmhpd SC8280XP_MMCX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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