df873243b2
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
53 lines
1.3 KiB
YAML
53 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
|
|
|
|
maintainers:
|
|
- Taniya Das <quic_tdas@quicinc.com>
|
|
- Imran Shaik <quic_imrashai@quicinc.com>
|
|
|
|
description: |
|
|
Qualcomm global clock control module which supports the clocks, resets and
|
|
power domains on QDU1000 and QRU1000
|
|
|
|
See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
|
|
|
|
properties:
|
|
compatible:
|
|
const: qcom,qdu1000-gcc
|
|
|
|
clocks:
|
|
items:
|
|
- description: Board XO source
|
|
- description: Sleep clock source
|
|
- description: PCIE 0 Pipe clock source
|
|
- description: PCIE 0 Phy Auxiliary clock source
|
|
- description: USB3 Phy wrapper pipe clock source
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
|
|
allOf:
|
|
- $ref: qcom,gcc.yaml#
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
clock-controller@100000 {
|
|
compatible = "qcom,qdu1000-gcc";
|
|
reg = <0x00100000 0x001f4200>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
|
|
<&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>,
|
|
<&usb3_phy_wrapper_pipe_clk>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|