ab7c01fdc3
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
74 lines
2.8 KiB
C
74 lines
2.8 KiB
C
/*
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* Copyright (C) 2004, 2007 Maciej W. Rozycki
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef _ASM_COMPILER_H
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#define _ASM_COMPILER_H
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/*
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* With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
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* compiler that a particular code path will never be hit. This allows it to be
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* optimised out of the generated binary.
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*
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* Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
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* that can lead to instructions from beyond an unreachable statement being
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* incorrectly reordered into earlier delay slots if the unreachable statement
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* is the only content of a case in a switch statement. This can lead to
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* seemingly random behaviour, such as invalid memory accesses from incorrectly
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* reordered loads or stores. See this potential GCC fix for details:
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*
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* https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
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*
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* It is unclear whether GCC 8 onwards suffer from the same issue - nothing
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* relevant is mentioned in GCC 8 release notes and nothing obviously relevant
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* stands out in GCC commit logs, but these newer GCC versions generate very
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* different code for the testcase which doesn't exhibit the bug.
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*
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* GCC also handles stack allocation suboptimally when calling noreturn
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* functions or calling __builtin_unreachable():
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*
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* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
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*
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* We work around both of these issues by placing a volatile asm statement,
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* which GCC is prevented from reordering past, prior to __builtin_unreachable
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* calls.
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*
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* The .insn statement is required to ensure that any branches to the
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* statement, which sadly must be kept due to the asm statement, are known to
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* be branches to code and satisfy linker requirements for microMIPS kernels.
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*/
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#undef barrier_before_unreachable
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#define barrier_before_unreachable() asm volatile(".insn")
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#if !defined(CONFIG_CC_IS_GCC) || \
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(__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
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# define GCC_OFF_SMALL_ASM() "ZC"
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#elif defined(CONFIG_CPU_MICROMIPS)
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# error "microMIPS compilation unsupported with GCC older than 4.9"
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#else
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# define GCC_OFF_SMALL_ASM() "R"
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#endif
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#ifdef CONFIG_CPU_MIPSR6
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#define MIPS_ISA_LEVEL "mips64r6"
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#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
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#define MIPS_ISA_LEVEL_RAW mips64r6
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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#elif defined(CONFIG_CPU_MIPSR5)
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#define MIPS_ISA_LEVEL "mips64r5"
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#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
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#define MIPS_ISA_LEVEL_RAW mips64r5
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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#else
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/* MIPS64 is a superset of MIPS32 */
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#define MIPS_ISA_LEVEL "mips64r2"
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#define MIPS_ISA_ARCH_LEVEL "arch=r4000"
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#define MIPS_ISA_LEVEL_RAW mips64r2
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* _ASM_COMPILER_H */
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