9ba9ad8f5b
We've discovered that disabling the so called Ethernet PLL causes reset of the devices consuming its outgoing clock. The resets happen automatically even if each underlying clock gate is turned off. Due to that we can't disable the Ethernet PLL until the kernel is prepared for the corresponding resets. So for now just mark the PLL clock provider as critical. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200920110335.18034-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| ccu-div.c | ||
| ccu-div.h | ||
| ccu-pll.c | ||
| ccu-pll.h | ||
| clk-ccu-div.c | ||
| clk-ccu-pll.c | ||
| Kconfig | ||
| Makefile | ||