Matt Redfearn 4f53989b06 MIPS: mm: Fix definition of R6 cache instruction
Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added
an incorrect definition of the redefined MIPSr6 cache instruction.

Executing any kernel code including this instuction results in a
reserved instruction exception and kernel panic.

Fix the instruction definition.

Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.x-
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-08-03 09:01:48 +02:00
..
2016-02-19 09:51:43 +01:00
2016-08-03 08:16:01 +02:00
2016-08-03 08:16:30 +02:00
2013-11-26 12:12:27 +01:00
2016-04-03 12:32:09 +02:00
2016-05-24 11:00:20 -07:00
2016-08-03 07:54:49 +02:00
2016-05-28 12:35:11 +02:00
2016-05-28 12:35:09 +02:00
2016-05-28 12:35:07 +02:00
2016-05-28 12:35:09 +02:00
2016-05-28 12:35:09 +02:00
2016-05-28 12:35:09 +02:00
2015-11-11 08:36:36 +01:00