d15befc0ce
When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Link: https://lore.kernel.org/r/20230919-spi-qup-dvfs-v2-3-1bac2e9ab8db@kernkonzept.com Signed-off-by: Mark Brown <broonie@kernel.org>
95 lines
2.3 KiB
YAML
95 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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The QUP core is an AHB slave that provides a common data path (an output FIFO
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and an input FIFO) for serial peripheral interface (SPI) mini-core.
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SPI in master mode supports up to 50MHz, up to four chip selects,
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programmable data path from 4 bits to 32 bits and numerous protocol variants.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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enum:
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- qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
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- qcom,spi-qup-v2.1.1 # for 8974 and later
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- qcom,spi-qup-v2.2.1 # for 8974 v2 and later
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: iface
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interconnects:
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maxItems: 1
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interrupts:
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maxItems: 1
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operating-points-v2: true
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/interconnect/qcom,msm8996.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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spi@7575000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x07575000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_spi1_default>;
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pinctrl-1 = <&blsp1_spi1_sleep>;
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dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
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dma-names = "tx", "rx";
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power-domains = <&rpmpd MSM8996_VDDCX>;
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operating-points-v2 = <&spi_opp_table>;
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interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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