c150b809f7
* Support for various vector-accelerated crypto routines. * Hibernation is now enabled for portable kernel builds. * mmap_rnd_bits_max is larger on systems with larger VAs. * Support for fast GUP. * Support for membarrier-based instruction cache synchronization. * Support for the Andes hart-level interrupt controller and PMU. * Some cleanups around unaligned access speed probing and Kconfig settings. * Support for ACPI LPI and CPPC. * Various cleanus related to barriers. * A handful of fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmX9icgTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYib+UD/4xyL6UMixx6A06BVBL9UT4vOrxRvNr JIihG5y5QNMjes9DHWL35mZTMqFtQ0tq94ViWFLmJWloV/8KRVM2C9R9KX7vplf3 M/OwvP106spxgvNHoeQbycgs42RU1t2mpqT7N1iK2hCjqieP3vLn6hsSLXWTAG0L 3gQbQw6XCLC3hPyLq+nbFY2i4faeCmpXWmixoy/IvQ5calZQrRU0LNlP6lcMBhVo uocjG0uGAhrahw2s81jxcMZcxa3AvUCiplapdD5H5v9rBM85SkYJj2Q9SqdSorkb xzuimRnKPI5s47yM3pTfZY0qnQUYHV7PXXuw4WujpCQVQdhaG+Ggq63UUZA61J9t IzZK2zdcfHqICrGTtXImUzRT3dcc3oq+IFq4tTY+rEJm29hrXkAtx+qBm5xtMvax fJz5feJ/iT0u7MDj4Oq24n+Kpl+Olm+MJaZX3m5Ovi/9V6a9iK9HXqxg9/Fs0fMO +J/0kTgd8Vu9CYH7KNWz3uztcO9eMAH3VyzuXuab4BGj1i1Y/9EjpALQi7rDN73S OsYQX6NnzMkBV4dvElJVLXiPlvNlMHZZwdak5CqPb48jaJu6iiIZAuvOrG6/naGP wnQSLVA2WWWoOkl3AJhxfpa11CLhbMl9E2gYm1VtNvASXoSFIxlAq1Yv3sG8yjty 4ZT0rYFJOstYiQ== =3dL5 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ...
185 lines
4.5 KiB
C
185 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#define pr_fmt(fmt) "suspend: " fmt
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#include <linux/ftrace.h>
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#include <linux/suspend.h>
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#include <asm/csr.h>
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#include <asm/sbi.h>
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#include <asm/suspend.h>
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void suspend_save_csrs(struct suspend_context *context)
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{
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context->scratch = csr_read(CSR_SCRATCH);
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if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
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context->envcfg = csr_read(CSR_ENVCFG);
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context->tvec = csr_read(CSR_TVEC);
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context->ie = csr_read(CSR_IE);
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/*
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* No need to save/restore IP CSR (i.e. MIP or SIP) because:
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*
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* 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
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* external devices (such as interrupt controller, timer, etc).
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* 2. For MMU (S-mode) kernel, the bits in SIP are set by
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* M-mode firmware and external devices (such as interrupt
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* controller, etc).
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*/
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#ifdef CONFIG_MMU
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context->satp = csr_read(CSR_SATP);
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#endif
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}
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void suspend_restore_csrs(struct suspend_context *context)
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{
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csr_write(CSR_SCRATCH, context->scratch);
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if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
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csr_write(CSR_ENVCFG, context->envcfg);
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csr_write(CSR_TVEC, context->tvec);
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csr_write(CSR_IE, context->ie);
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#ifdef CONFIG_MMU
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csr_write(CSR_SATP, context->satp);
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#endif
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}
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int cpu_suspend(unsigned long arg,
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int (*finish)(unsigned long arg,
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unsigned long entry,
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unsigned long context))
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{
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int rc = 0;
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struct suspend_context context = { 0 };
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/* Finisher should be non-NULL */
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if (!finish)
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return -EINVAL;
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/* Save additional CSRs*/
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suspend_save_csrs(&context);
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/*
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* Function graph tracer state gets incosistent when the kernel
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* calls functions that never return (aka finishers) hence disable
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* graph tracing during their execution.
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*/
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pause_graph_tracing();
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/* Save context on stack */
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if (__cpu_suspend_enter(&context)) {
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/* Call the finisher */
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rc = finish(arg, __pa_symbol(__cpu_resume_enter),
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(ulong)&context);
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/*
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* Should never reach here, unless the suspend finisher
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* fails. Successful cpu_suspend() should return from
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* __cpu_resume_entry()
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*/
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if (!rc)
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rc = -EOPNOTSUPP;
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}
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/* Enable function graph tracer */
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unpause_graph_tracing();
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/* Restore additional CSRs */
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suspend_restore_csrs(&context);
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return rc;
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}
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#ifdef CONFIG_RISCV_SBI
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static int sbi_system_suspend(unsigned long sleep_type,
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unsigned long resume_addr,
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unsigned long opaque)
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{
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struct sbiret ret;
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ret = sbi_ecall(SBI_EXT_SUSP, SBI_EXT_SUSP_SYSTEM_SUSPEND,
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sleep_type, resume_addr, opaque, 0, 0, 0);
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if (ret.error)
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return sbi_err_map_linux_errno(ret.error);
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return ret.value;
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}
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static int sbi_system_suspend_enter(suspend_state_t state)
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{
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return cpu_suspend(SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM, sbi_system_suspend);
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}
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static const struct platform_suspend_ops sbi_system_suspend_ops = {
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.valid = suspend_valid_only_mem,
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.enter = sbi_system_suspend_enter,
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};
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static int __init sbi_system_suspend_init(void)
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{
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if (sbi_spec_version >= sbi_mk_version(2, 0) &&
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sbi_probe_extension(SBI_EXT_SUSP) > 0) {
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pr_info("SBI SUSP extension detected\n");
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if (IS_ENABLED(CONFIG_SUSPEND))
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suspend_set_ops(&sbi_system_suspend_ops);
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}
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return 0;
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}
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arch_initcall(sbi_system_suspend_init);
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static int sbi_suspend_finisher(unsigned long suspend_type,
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unsigned long resume_addr,
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unsigned long opaque)
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{
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struct sbiret ret;
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ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND,
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suspend_type, resume_addr, opaque, 0, 0, 0);
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return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0;
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}
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int riscv_sbi_hart_suspend(u32 state)
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{
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if (state & SBI_HSM_SUSP_NON_RET_BIT)
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return cpu_suspend(state, sbi_suspend_finisher);
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else
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return sbi_suspend_finisher(state, 0, 0);
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}
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bool riscv_sbi_suspend_state_is_valid(u32 state)
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{
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if (state > SBI_HSM_SUSPEND_RET_DEFAULT &&
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state < SBI_HSM_SUSPEND_RET_PLATFORM)
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return false;
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if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT &&
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state < SBI_HSM_SUSPEND_NON_RET_PLATFORM)
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return false;
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return true;
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}
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bool riscv_sbi_hsm_is_supported(void)
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{
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/*
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* The SBI HSM suspend function is only available when:
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* 1) SBI version is 0.3 or higher
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* 2) SBI HSM extension is available
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*/
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if (sbi_spec_version < sbi_mk_version(0, 3) ||
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!sbi_probe_extension(SBI_EXT_HSM)) {
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pr_info("HSM suspend not available\n");
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return false;
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}
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return true;
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}
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#endif /* CONFIG_RISCV_SBI */
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