Yash Shah 507308b8cc
RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-01-07 17:28:27 -08:00
..
2020-12-24 12:18:11 -08:00
2020-12-24 12:28:35 -08:00
2020-12-16 16:38:41 -08:00
2020-12-18 12:38:28 -08:00
2020-12-16 16:38:41 -08:00
2020-12-24 12:18:11 -08:00
2020-12-17 12:52:23 -08:00
2020-12-24 12:14:29 -08:00
2020-12-15 16:06:14 -08:00
2020-12-16 11:49:46 -08:00
2020-12-15 16:30:31 -08:00
2021-01-01 12:58:07 -08:00
2020-12-16 13:58:47 -08:00
2020-12-20 10:44:05 -08:00
2020-12-09 19:26:02 -06:00
2020-12-16 16:38:41 -08:00
2020-12-16 13:34:31 -08:00
2020-12-17 13:34:25 -08:00
2020-12-15 15:57:25 -08:00
2020-12-16 13:42:26 -08:00
2020-12-15 14:02:26 -08:00
2020-12-25 20:17:40 -08:00
2020-12-23 15:06:22 -08:00
2020-12-15 22:50:12 +11:00
2020-12-19 11:51:32 -08:00
2020-12-16 16:38:41 -08:00
2020-12-16 16:38:41 -08:00
2020-12-20 10:12:06 -08:00
2020-12-24 12:28:35 -08:00
2021-01-01 12:58:07 -08:00
2020-12-10 10:45:36 +01:00
2020-12-18 12:38:28 -08:00
2020-12-16 13:34:31 -08:00
2020-12-16 16:38:41 -08:00
2020-12-17 13:41:27 -08:00
2020-12-17 13:34:25 -08:00
2020-12-20 10:44:05 -08:00
2020-12-18 12:38:28 -08:00
2020-12-09 19:44:34 +01:00
2020-12-23 15:01:49 -08:00