Antoine Tenart 515f1a2027 clk: berlin: add cpuclk ...

Add cpuclk in the Berlin BG2Q clock driver. This clk has a divider
fixed to 1.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

2015-10-15 20:55:55 +02:00

..

berlin2-avpll.c

…

berlin2-avpll.h

…

berlin2-div.c

clk: berlin: add driver for BG2x complex divider cells

2014-05-29 09:30:18 -07:00

berlin2-div.h

clk: berlin: add driver for BG2x complex divider cells

2014-05-29 09:30:18 -07:00

berlin2-pll.c

clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

2015-08-24 16:49:12 -07:00

berlin2-pll.h

…

bg2.c

clk: berlin: drop direct of_iomap of nodes reg property

2015-05-18 18:10:13 +02:00

bg2q.c

clk: berlin: add cpuclk

2015-10-15 20:55:55 +02:00

common.h

clk: berlin: add core clock driver for BG2/BG2CD

2014-05-29 09:30:19 -07:00

Makefile

clk: berlin: add core clock driver for BG2Q

2014-05-29 09:30:19 -07:00