David S. Miller 517af33237 [SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section.  The default uses
virtual addresses, and the patch instructions use physical
address load/stores.

We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:32 -08:00
..
2006-03-06 18:40:44 -08:00
2006-03-16 16:55:08 +11:00
2006-02-24 14:31:37 -08:00
2006-03-06 18:40:44 -08:00