Yong Zhao 51ac7eec62 drm/amdgpu: Support IOMMU on Raven
We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for
PDEs and setting S bit to 1 for PTEs when the corresponding addresses
are not occupied by gpu driver allocated buffers.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-15 14:45:58 -04:00
..
2017-03-14 19:19:44 -04:00
2017-08-15 14:45:58 -04:00