675398674c
It costs expensive to change clock configuration for models of protocol version 3. In current implementation, speculative strategy is used to finish the operation; just waiting for 4 seconds. As long as I investigate, when accepting and changing clock status actually, the device sends notification with mask. This commit uses wise way to wait for the notification after changing sampling clock rate during 4 seconds. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Link: https://lore.kernel.org/r/20200614141221.53527-1-o-takashi@sakamocchi.jp Signed-off-by: Takashi Iwai <tiwai@suse.de>
327 lines
7.7 KiB
C
327 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* motu-protocol-v3.c - a part of driver for MOTU FireWire series
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*
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* Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
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*/
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#include <linux/delay.h>
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#include "motu.h"
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#define V3_CLOCK_STATUS_OFFSET 0x0b14
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#define V3_FETCH_PCM_FRAMES 0x02000000
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#define V3_CLOCK_RATE_MASK 0x0000ff00
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#define V3_CLOCK_RATE_SHIFT 8
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#define V3_CLOCK_SOURCE_MASK 0x000000ff
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#define V3_OPT_IFACE_MODE_OFFSET 0x0c94
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#define V3_ENABLE_OPT_IN_IFACE_A 0x00000001
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#define V3_ENABLE_OPT_IN_IFACE_B 0x00000002
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#define V3_ENABLE_OPT_OUT_IFACE_A 0x00000100
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#define V3_ENABLE_OPT_OUT_IFACE_B 0x00000200
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#define V3_NO_ADAT_OPT_IN_IFACE_A 0x00010000
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#define V3_NO_ADAT_OPT_IN_IFACE_B 0x00100000
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#define V3_NO_ADAT_OPT_OUT_IFACE_A 0x00040000
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#define V3_NO_ADAT_OPT_OUT_IFACE_B 0x00400000
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#define V3_MSG_FLAG_CLK_CHANGED 0x00000002
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#define V3_CLK_WAIT_MSEC 4000
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int snd_motu_protocol_v3_get_clock_rate(struct snd_motu *motu,
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unsigned int *rate)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data = (data & V3_CLOCK_RATE_MASK) >> V3_CLOCK_RATE_SHIFT;
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if (data >= ARRAY_SIZE(snd_motu_clock_rates))
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return -EIO;
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*rate = snd_motu_clock_rates[data];
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return 0;
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}
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int snd_motu_protocol_v3_set_clock_rate(struct snd_motu *motu,
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unsigned int rate)
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{
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__be32 reg;
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u32 data;
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bool need_to_wait;
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int i, err;
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for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
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if (snd_motu_clock_rates[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(snd_motu_clock_rates))
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return -EINVAL;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~(V3_CLOCK_RATE_MASK | V3_FETCH_PCM_FRAMES);
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data |= i << V3_CLOCK_RATE_SHIFT;
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need_to_wait = data != be32_to_cpu(reg);
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reg = cpu_to_be32(data);
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err = snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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if (need_to_wait) {
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int result;
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motu->msg = 0;
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result = wait_event_interruptible_timeout(motu->hwdep_wait,
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motu->msg & V3_MSG_FLAG_CLK_CHANGED,
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msecs_to_jiffies(V3_CLK_WAIT_MSEC));
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if (result < 0)
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return result;
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if (result == 0)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int detect_clock_source_828mk3(struct snd_motu *motu, u32 data,
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enum snd_motu_clock_source *src)
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{
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switch (data) {
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case 0x00:
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*src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
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break;
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case 0x01:
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*src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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break;
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case 0x02:
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*src = SND_MOTU_CLOCK_SOURCE_SPH;
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break;
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case 0x10:
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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break;
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case 0x18:
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case 0x19:
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{
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__be32 reg;
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u32 options;
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int err;
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err = snd_motu_transaction_read(motu,
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V3_OPT_IFACE_MODE_OFFSET, ®, sizeof(reg));
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if (err < 0)
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return err;
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options = be32_to_cpu(reg);
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if (data == 0x18) {
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if (options & V3_NO_ADAT_OPT_IN_IFACE_A)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_A;
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else
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_A;
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} else {
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if (options & V3_NO_ADAT_OPT_IN_IFACE_B)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_B;
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else
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_B;
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}
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break;
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}
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default:
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*src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
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break;
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}
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return 0;
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}
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static int v3_detect_clock_source(struct snd_motu *motu, u32 data,
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enum snd_motu_clock_source *src)
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{
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switch (data) {
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case 0x00:
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*src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
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break;
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case 0x01:
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*src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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break;
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case 0x02:
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*src = SND_MOTU_CLOCK_SOURCE_SPH;
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break;
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case 0x10:
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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break;
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default:
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*src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
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break;
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}
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return 0;
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}
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int snd_motu_protocol_v3_get_clock_source(struct snd_motu *motu,
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enum snd_motu_clock_source *src)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg) & V3_CLOCK_SOURCE_MASK;
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if (motu->spec == &snd_motu_spec_828mk3)
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return detect_clock_source_828mk3(motu, data, src);
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else
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return v3_detect_clock_source(motu, data, src);
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}
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int snd_motu_protocol_v3_switch_fetching_mode(struct snd_motu *motu,
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bool enable)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return 0;
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data = be32_to_cpu(reg);
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if (enable)
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data |= V3_FETCH_PCM_FRAMES;
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else
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data &= ~V3_FETCH_PCM_FRAMES;
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static int detect_packet_formats_828mk3(struct snd_motu *motu, u32 data)
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{
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if (data & V3_ENABLE_OPT_IN_IFACE_A) {
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if (data & V3_NO_ADAT_OPT_IN_IFACE_A) {
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motu->tx_packet_formats.pcm_chunks[0] += 4;
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motu->tx_packet_formats.pcm_chunks[1] += 4;
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} else {
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motu->tx_packet_formats.pcm_chunks[0] += 8;
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motu->tx_packet_formats.pcm_chunks[1] += 4;
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}
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}
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if (data & V3_ENABLE_OPT_IN_IFACE_B) {
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if (data & V3_NO_ADAT_OPT_IN_IFACE_B) {
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motu->tx_packet_formats.pcm_chunks[0] += 4;
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motu->tx_packet_formats.pcm_chunks[1] += 4;
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} else {
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motu->tx_packet_formats.pcm_chunks[0] += 8;
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motu->tx_packet_formats.pcm_chunks[1] += 4;
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}
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}
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if (data & V3_ENABLE_OPT_OUT_IFACE_A) {
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if (data & V3_NO_ADAT_OPT_OUT_IFACE_A) {
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motu->rx_packet_formats.pcm_chunks[0] += 4;
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motu->rx_packet_formats.pcm_chunks[1] += 4;
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} else {
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motu->rx_packet_formats.pcm_chunks[0] += 8;
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motu->rx_packet_formats.pcm_chunks[1] += 4;
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}
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}
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if (data & V3_ENABLE_OPT_OUT_IFACE_B) {
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if (data & V3_NO_ADAT_OPT_OUT_IFACE_B) {
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motu->rx_packet_formats.pcm_chunks[0] += 4;
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motu->rx_packet_formats.pcm_chunks[1] += 4;
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} else {
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motu->rx_packet_formats.pcm_chunks[0] += 8;
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motu->rx_packet_formats.pcm_chunks[1] += 4;
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}
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}
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return 0;
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}
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int snd_motu_protocol_v3_cache_packet_formats(struct snd_motu *motu)
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{
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__be32 reg;
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u32 data;
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int err;
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motu->tx_packet_formats.pcm_byte_offset = 10;
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motu->rx_packet_formats.pcm_byte_offset = 10;
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motu->tx_packet_formats.msg_chunks = 2;
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motu->rx_packet_formats.msg_chunks = 2;
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err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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memcpy(motu->tx_packet_formats.pcm_chunks,
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motu->spec->tx_fixed_pcm_chunks,
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sizeof(motu->tx_packet_formats.pcm_chunks));
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memcpy(motu->rx_packet_formats.pcm_chunks,
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motu->spec->rx_fixed_pcm_chunks,
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sizeof(motu->rx_packet_formats.pcm_chunks));
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if (motu->spec == &snd_motu_spec_828mk3)
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return detect_packet_formats_828mk3(motu, data);
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else
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return 0;
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}
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const struct snd_motu_spec snd_motu_spec_828mk3 = {
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.name = "828mk3",
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.protocol_version = SND_MOTU_PROTOCOL_V3,
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.flags = SND_MOTU_SPEC_RX_MIDI_3RD_Q |
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SND_MOTU_SPEC_TX_MIDI_3RD_Q,
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.tx_fixed_pcm_chunks = {18, 18, 14},
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.rx_fixed_pcm_chunks = {14, 14, 10},
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};
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const struct snd_motu_spec snd_motu_spec_ultralite_mk3 = {
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.name = "UltraLiteMk3",
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.protocol_version = SND_MOTU_PROTOCOL_V3,
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.flags = SND_MOTU_SPEC_RX_MIDI_3RD_Q |
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SND_MOTU_SPEC_TX_MIDI_3RD_Q,
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.tx_fixed_pcm_chunks = {18, 14, 10},
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.rx_fixed_pcm_chunks = {14, 14, 14},
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};
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const struct snd_motu_spec snd_motu_spec_audio_express = {
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.name = "AudioExpress",
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.protocol_version = SND_MOTU_PROTOCOL_V3,
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.flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
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SND_MOTU_SPEC_TX_MIDI_3RD_Q,
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.tx_fixed_pcm_chunks = {10, 10, 0},
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.rx_fixed_pcm_chunks = {10, 10, 0},
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};
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const struct snd_motu_spec snd_motu_spec_4pre = {
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.name = "4pre",
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.protocol_version = SND_MOTU_PROTOCOL_V3,
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.tx_fixed_pcm_chunks = {10, 10, 0},
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.rx_fixed_pcm_chunks = {10, 10, 0},
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};
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