Weiyi Lu 51ff86dd10 clk: mediatek: update clock driver of MT2712
According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05 13:28:04 -08:00
..