James Zhu 5326ad54c5 drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled ...

When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-05-24 12:20:50 -05:00

..

acp

drm/amdgpu: Remove wrapper layer of cgs irq handling

2018-03-21 14:36:58 -05:00

amdgpu

drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled

2019-05-24 12:20:50 -05:00

amdkfd

drm/amdkfd: Cosmetic cleanup

2019-05-24 12:20:48 -05:00

display

drm/amd/display: Expose send immediate sdp message interface

2019-05-24 12:20:50 -05:00

include

drm/amdgpu: add EDC counter register

2019-05-24 12:20:50 -05:00

powerplay

drm/amd/powerplay: expose SMU7 asics realtime memory utilization

2019-05-24 12:20:48 -05:00