linux/drivers/cxl
Ben Widawsky 538831f1be cxl/hdm: Add sysfs attributes for interleave ways + granularity
The region provisioning flow involves selecting interleave ways +
granularity settings for a region, and then programming the decoder
topology to meet those constraints, if possible. For example, root
decoders set the minimum interleave ways + granularity for any hosted
regions.

Given decoder programming is not atomic and collisions can occur between
multiple requesting regions userspace will be responsible for conflict
resolution and it needs these attributes to make those decisions.

Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784332235.1758207.7185062713652694607.stgit@dwillia2-xfh.jf.intel.com
[djbw: reword changelog, make read-only, add sysfs ABI documentaion]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-07-21 17:19:25 -07:00
..
core cxl/hdm: Add sysfs attributes for interleave ways + granularity 2022-07-21 17:19:25 -07:00
acpi.c cxl/port: Record parent dport when adding ports 2022-07-21 17:19:24 -07:00
cxl.h cxl/port: Move dport tracking to an xarray 2022-07-21 17:19:24 -07:00
cxlmem.h cxl/hdm: Enumerate allocated DPA 2022-07-21 17:19:12 -07:00
cxlpci.h cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00
Kconfig cxl/pci: Create PCI DOE mailbox's for memory devices 2022-07-19 15:38:04 -07:00
Makefile PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
mem.c cxl/port: Record parent dport when adding ports 2022-07-21 17:19:24 -07:00
pci.c cxl/pci: Create PCI DOE mailbox's for memory devices 2022-07-19 15:38:04 -07:00
pmem.c cxl/mbox: Use __le32 in get,set_lsa mailbox structures 2022-06-21 14:09:00 -07:00
port.c cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00