96765cc475
Add a function to set the ERD (Error Response Disable) bit in the MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error handler driver. ERD bit allows masking of SError due to inband errors which are caused by illegal register accesses through CBB. When the bit is set, interrupt is used for reporting errors and magic code '0xdead2003' is returned. This change is only required for Tegra194 SoC as the config is moved to CBB register space for future SoC's. Also, remove unmapping the apbmisc_base as it's required to get the base address for accessing the misc register. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
111 lines
2.0 KiB
C
111 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __SOC_TEGRA_FUSE_H__
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#define __SOC_TEGRA_FUSE_H__
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#include <linux/types.h>
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#define TEGRA20 0x20
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#define TEGRA30 0x30
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#define TEGRA114 0x35
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#define TEGRA124 0x40
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#define TEGRA132 0x13
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#define TEGRA210 0x21
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#define TEGRA186 0x18
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#define TEGRA194 0x19
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#define TEGRA234 0x23
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#define TEGRA_FUSE_SKU_CALIB_0 0xf0
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#define TEGRA30_FUSE_SATA_CALIB 0x124
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#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
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#ifndef __ASSEMBLY__
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enum tegra_revision {
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TEGRA_REVISION_UNKNOWN = 0,
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TEGRA_REVISION_A01,
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TEGRA_REVISION_A02,
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TEGRA_REVISION_A03,
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TEGRA_REVISION_A03p,
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TEGRA_REVISION_A04,
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TEGRA_REVISION_MAX,
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};
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struct tegra_sku_info {
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int sku_id;
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int cpu_process_id;
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int cpu_speedo_id;
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int cpu_speedo_value;
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int cpu_iddq_value;
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int soc_process_id;
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int soc_speedo_id;
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int soc_speedo_value;
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int gpu_process_id;
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int gpu_speedo_id;
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int gpu_speedo_value;
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enum tegra_revision revision;
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};
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#ifdef CONFIG_ARCH_TEGRA
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extern struct tegra_sku_info tegra_sku_info;
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u32 tegra_read_straps(void);
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u32 tegra_read_ram_code(void);
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int tegra_fuse_readl(unsigned long offset, u32 *value);
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u32 tegra_read_chipid(void);
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u8 tegra_get_chip_id(void);
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u8 tegra_get_platform(void);
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bool tegra_is_silicon(void);
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int tegra194_miscreg_mask_serror(void);
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#else
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static struct tegra_sku_info tegra_sku_info __maybe_unused;
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static inline u32 tegra_read_straps(void)
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{
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return 0;
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}
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static inline u32 tegra_read_ram_code(void)
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{
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return 0;
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}
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static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
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{
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return -ENODEV;
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}
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static inline u32 tegra_read_chipid(void)
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{
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return 0;
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}
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static inline u8 tegra_get_chip_id(void)
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{
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return 0;
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}
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static inline u8 tegra_get_platform(void)
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{
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return 0;
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}
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static inline bool tegra_is_silicon(void)
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{
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return false;
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}
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static inline int tegra194_miscreg_mask_serror(void)
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{
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return false;
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}
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#endif
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struct device *tegra_soc_device_register(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __SOC_TEGRA_FUSE_H__ */
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