92508e7fcf
Scatter Gather input format for CPT has changed on CN10KB/CN10KA B0 HW to make it compatible with NIX Scatter Gather format to support SG mode for inline IPsec. This patch modifies the code to make the driver works for the same. This patch also enables CPT firmware load for these chips. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __OTX2_CPTVF_H
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#define __OTX2_CPTVF_H
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#include "mbox.h"
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#include "otx2_cptlf.h"
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struct otx2_cptvf_dev {
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void __iomem *reg_base; /* Register start address */
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void __iomem *pfvf_mbox_base; /* PF-VF mbox start address */
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struct pci_dev *pdev; /* PCI device handle */
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struct otx2_cptlfs_info lfs; /* CPT LFs attached to this VF */
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u8 vf_id; /* Virtual function index */
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/* PF <=> VF mbox */
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struct otx2_mbox pfvf_mbox;
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struct work_struct pfvf_mbox_work;
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struct workqueue_struct *pfvf_mbox_wq;
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int blkaddr;
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void *bbuf_base;
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unsigned long cap_flag;
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u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES];
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};
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irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);
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void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work);
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int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);
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int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);
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int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev);
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int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf);
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#endif /* __OTX2_CPTVF_H */
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