5636d2f842
The GART table BO has to be moved out of VRAM for suspend/resume. Any updates to the GART table during that time were silently dropped without this change. This caused GPU lockups on resume in some cases, see the bug reports referenced below. This might also make GPU reset more robust in some cases, as we no longer rely on the GART table in VRAM being preserved across the GPU lockup/reset. v2: Add logic to radeon_gart_table_vram_pin directly instead of reinstating radeon_gart_restore v3: Move code after assignment of rdev->gart.table_addr so that the GART TLB flush can work as intended, add code comment explaining why we're doing this Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85204 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86267 Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
393 lines
11 KiB
C
393 lines
11 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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/*
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* GART
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* The GART (Graphics Aperture Remapping Table) is an aperture
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* in the GPU's address space. System pages can be mapped into
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* the aperture and look like contiguous pages from the GPU's
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* perspective. A page table maps the pages in the aperture
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* to the actual backing pages in system memory.
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*
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* Radeon GPUs support both an internal GART, as described above,
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* and AGP. AGP works similarly, but the GART table is configured
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* and maintained by the northbridge rather than the driver.
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* Radeon hw has a separate AGP aperture that is programmed to
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* point to the AGP aperture provided by the northbridge and the
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* requests are passed through to the northbridge aperture.
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* Both AGP and internal GART can be used at the same time, however
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* that is not currently supported by the driver.
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*
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* This file handles the common internal GART management.
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*/
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/*
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* Common GART table functions.
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*/
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/**
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* radeon_gart_table_ram_alloc - allocate system ram for gart page table
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*
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* @rdev: radeon_device pointer
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*
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* Allocate system memory for GART page table
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* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
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* gart table to be in system memory.
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* Returns 0 for success, -ENOMEM for failure.
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*/
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int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
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{
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void *ptr;
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ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
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&rdev->gart.table_addr);
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if (ptr == NULL) {
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return -ENOMEM;
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}
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#ifdef CONFIG_X86
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
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rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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set_memory_uc((unsigned long)ptr,
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rdev->gart.table_size >> PAGE_SHIFT);
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}
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#endif
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rdev->gart.ptr = ptr;
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memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
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return 0;
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}
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/**
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* radeon_gart_table_ram_free - free system ram for gart page table
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*
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* @rdev: radeon_device pointer
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*
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* Free system memory for GART page table
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* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
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* gart table to be in system memory.
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*/
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void radeon_gart_table_ram_free(struct radeon_device *rdev)
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{
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if (rdev->gart.ptr == NULL) {
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return;
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}
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#ifdef CONFIG_X86
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
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rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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set_memory_wb((unsigned long)rdev->gart.ptr,
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rdev->gart.table_size >> PAGE_SHIFT);
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}
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#endif
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pci_free_consistent(rdev->pdev, rdev->gart.table_size,
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(void *)rdev->gart.ptr,
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rdev->gart.table_addr);
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rdev->gart.ptr = NULL;
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rdev->gart.table_addr = 0;
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}
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/**
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* radeon_gart_table_vram_alloc - allocate vram for gart page table
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*
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* @rdev: radeon_device pointer
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*
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* Allocate video memory for GART page table
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* (pcie r4xx, r5xx+). These asics require the
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* gart table to be in video memory.
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* Returns 0 for success, error for failure.
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*/
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int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.robj == NULL) {
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r = radeon_bo_create(rdev, rdev->gart.table_size,
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PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
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0, NULL, NULL, &rdev->gart.robj);
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if (r) {
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return r;
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}
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}
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return 0;
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}
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/**
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* radeon_gart_table_vram_pin - pin gart page table in vram
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*
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* @rdev: radeon_device pointer
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*
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* Pin the GART page table in vram so it will not be moved
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* by the memory manager (pcie r4xx, r5xx+). These asics require the
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* gart table to be in video memory.
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* Returns 0 for success, error for failure.
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*/
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int radeon_gart_table_vram_pin(struct radeon_device *rdev)
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{
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uint64_t gpu_addr;
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int r;
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r = radeon_bo_reserve(rdev->gart.robj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_pin(rdev->gart.robj,
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RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->gart.robj);
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return r;
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}
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r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
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if (r)
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radeon_bo_unpin(rdev->gart.robj);
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radeon_bo_unreserve(rdev->gart.robj);
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rdev->gart.table_addr = gpu_addr;
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if (!r) {
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int i;
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/* We might have dropped some GART table updates while it wasn't
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* mapped, restore all entries
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*/
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for (i = 0; i < rdev->gart.num_gpu_pages; i++)
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radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
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mb();
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radeon_gart_tlb_flush(rdev);
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}
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return r;
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}
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/**
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* radeon_gart_table_vram_unpin - unpin gart page table in vram
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*
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* @rdev: radeon_device pointer
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*
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* Unpin the GART page table in vram (pcie r4xx, r5xx+).
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* These asics require the gart table to be in video memory.
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*/
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void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.robj == NULL) {
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return;
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}
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r = radeon_bo_reserve(rdev->gart.robj, false);
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if (likely(r == 0)) {
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radeon_bo_kunmap(rdev->gart.robj);
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radeon_bo_unpin(rdev->gart.robj);
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radeon_bo_unreserve(rdev->gart.robj);
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rdev->gart.ptr = NULL;
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}
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}
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/**
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* radeon_gart_table_vram_free - free gart page table vram
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*
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* @rdev: radeon_device pointer
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*
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* Free the video memory used for the GART page table
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* (pcie r4xx, r5xx+). These asics require the gart table to
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* be in video memory.
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*/
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void radeon_gart_table_vram_free(struct radeon_device *rdev)
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{
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if (rdev->gart.robj == NULL) {
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return;
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}
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radeon_bo_unref(&rdev->gart.robj);
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}
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/*
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* Common gart functions.
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*/
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/**
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* radeon_gart_unbind - unbind pages from the gart page table
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*
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* @rdev: radeon_device pointer
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* @offset: offset into the GPU's gart aperture
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* @pages: number of pages to unbind
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*
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* Unbinds the requested pages from the gart page table and
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* replaces them with the dummy page (all asics).
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*/
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void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
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int pages)
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{
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unsigned t;
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unsigned p;
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int i, j;
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if (!rdev->gart.ready) {
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WARN(1, "trying to unbind memory from uninitialized GART !\n");
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return;
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}
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t = offset / RADEON_GPU_PAGE_SIZE;
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p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
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for (i = 0; i < pages; i++, p++) {
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if (rdev->gart.pages[p]) {
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rdev->gart.pages[p] = NULL;
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rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
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if (rdev->gart.ptr) {
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radeon_gart_set_page(rdev, t,
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rdev->dummy_page.entry);
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}
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}
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}
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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}
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/**
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* radeon_gart_bind - bind pages into the gart page table
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*
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* @rdev: radeon_device pointer
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* @offset: offset into the GPU's gart aperture
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* @pages: number of pages to bind
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* @pagelist: pages to bind
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* @dma_addr: DMA addresses of pages
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* @flags: RADEON_GART_PAGE_* flags
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*
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* Binds the requested pages to the gart page table
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* (all asics).
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* Returns 0 for success, -EINVAL for failure.
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*/
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int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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int pages, struct page **pagelist, dma_addr_t *dma_addr,
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uint32_t flags)
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{
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unsigned t;
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unsigned p;
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uint64_t page_base, page_entry;
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int i, j;
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if (!rdev->gart.ready) {
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WARN(1, "trying to bind memory to uninitialized GART !\n");
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return -EINVAL;
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}
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t = offset / RADEON_GPU_PAGE_SIZE;
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p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
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for (i = 0; i < pages; i++, p++) {
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rdev->gart.pages_addr[p] = dma_addr[i];
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rdev->gart.pages[p] = pagelist[i];
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page_base = dma_addr[i];
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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page_entry = radeon_gart_get_page_entry(page_base, flags);
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rdev->gart.pages_entry[t] = page_entry;
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if (rdev->gart.ptr) {
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radeon_gart_set_page(rdev, t, page_entry);
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}
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page_base += RADEON_GPU_PAGE_SIZE;
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}
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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return 0;
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}
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/**
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* radeon_gart_init - init the driver info for managing the gart
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*
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* @rdev: radeon_device pointer
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*
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* Allocate the dummy page and init the gart driver info (all asics).
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* Returns 0 for success, error for failure.
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*/
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int radeon_gart_init(struct radeon_device *rdev)
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{
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int r, i;
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if (rdev->gart.pages) {
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return 0;
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}
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/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
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if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
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DRM_ERROR("Page size is smaller than GPU page size!\n");
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return -EINVAL;
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}
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r = radeon_dummy_page_init(rdev);
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if (r)
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return r;
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/* Compute table size */
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rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
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rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
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DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
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rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
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/* Allocate pages table */
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rdev->gart.pages = vzalloc(sizeof(void *) * rdev->gart.num_cpu_pages);
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if (rdev->gart.pages == NULL) {
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radeon_gart_fini(rdev);
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return -ENOMEM;
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}
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rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
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rdev->gart.num_cpu_pages);
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if (rdev->gart.pages_addr == NULL) {
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radeon_gart_fini(rdev);
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return -ENOMEM;
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}
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rdev->gart.pages_entry = vmalloc(sizeof(uint64_t) *
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rdev->gart.num_gpu_pages);
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if (rdev->gart.pages_entry == NULL) {
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radeon_gart_fini(rdev);
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return -ENOMEM;
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}
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/* set GART entry to point to the dummy page by default */
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for (i = 0; i < rdev->gart.num_cpu_pages; i++)
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rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
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for (i = 0; i < rdev->gart.num_gpu_pages; i++)
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rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
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return 0;
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}
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/**
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* radeon_gart_fini - tear down the driver info for managing the gart
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*
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* @rdev: radeon_device pointer
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*
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* Tear down the gart driver info and free the dummy page (all asics).
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*/
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void radeon_gart_fini(struct radeon_device *rdev)
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{
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if (rdev->gart.ready) {
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/* unbind pages */
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radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
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}
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rdev->gart.ready = false;
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vfree(rdev->gart.pages);
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vfree(rdev->gart.pages_addr);
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vfree(rdev->gart.pages_entry);
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rdev->gart.pages = NULL;
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rdev->gart.pages_addr = NULL;
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rdev->gart.pages_entry = NULL;
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radeon_dummy_page_fini(rdev);
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}
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