5694cecdb0
In the end, we ended up with quite a lot more than I expected: - Support for ARMv8.3 Pointer Authentication in userspace (CRIU and kernel-side support to come later) - Support for per-thread stack canaries, pending an update to GCC that is currently undergoing review - Support for kexec_file_load(), which permits secure boot of a kexec payload but also happens to improve the performance of kexec dramatically because we can avoid the sucky purgatory code from userspace. Kdump will come later (requires updates to libfdt). - Optimisation of our dynamic CPU feature framework, so that all detected features are enabled via a single stop_machine() invocation - KPTI whitelisting of Cortex-A CPUs unaffected by Meltdown, so that they can benefit from global TLB entries when KASLR is not in use - 52-bit virtual addressing for userspace (kernel remains 48-bit) - Patch in LSE atomics for per-cpu atomic operations - Custom preempt.h implementation to avoid unconditional calls to preempt_schedule() from preempt_enable() - Support for the new 'SB' Speculation Barrier instruction - Vectorised implementation of XOR checksumming and CRC32 optimisations - Workaround for Cortex-A76 erratum #1165522 - Improved compatibility with Clang/LLD - Support for TX2 system PMUS for profiling the L3 cache and DMC - Reflect read-only permissions in the linear map by default - Ensure MMIO reads are ordered with subsequent calls to Xdelay() - Initial support for memory hotplug - Tweak the threshold when we invalidate the TLB by-ASID, so that mremap() performance is improved for ranges spanning multiple PMDs. - Minor refactoring and cleanups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJcE4TmAAoJELescNyEwWM0Nr0H/iaU7/wQSzHyNXtZoImyKTul Blu2ga4/EqUrTU7AVVfmkl/3NBILWlgQVpY6tH6EfXQuvnxqD7CizbHyLdyO+z0S B5PsFUH2GLMNAi48AUNqGqkgb2knFbg+T+9IimijDBkKg1G/KhQnRg6bXX32mLJv Une8oshUPBVJMsHN1AcQknzKariuoE3u0SgJ+eOZ9yA2ZwKxP4yy1SkDt3xQrtI0 lojeRjxcyjTP1oGRNZC+BWUtGOT35p7y6cGTnBd/4TlqBGz5wVAJUcdoxnZ6JYVR O8+ob9zU+4I0+SKt80s7pTLqQiL9rxkKZ5joWK1pr1g9e0s5N5yoETXKFHgJYP8= =sYdt -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 festive updates from Will Deacon: "In the end, we ended up with quite a lot more than I expected: - Support for ARMv8.3 Pointer Authentication in userspace (CRIU and kernel-side support to come later) - Support for per-thread stack canaries, pending an update to GCC that is currently undergoing review - Support for kexec_file_load(), which permits secure boot of a kexec payload but also happens to improve the performance of kexec dramatically because we can avoid the sucky purgatory code from userspace. Kdump will come later (requires updates to libfdt). - Optimisation of our dynamic CPU feature framework, so that all detected features are enabled via a single stop_machine() invocation - KPTI whitelisting of Cortex-A CPUs unaffected by Meltdown, so that they can benefit from global TLB entries when KASLR is not in use - 52-bit virtual addressing for userspace (kernel remains 48-bit) - Patch in LSE atomics for per-cpu atomic operations - Custom preempt.h implementation to avoid unconditional calls to preempt_schedule() from preempt_enable() - Support for the new 'SB' Speculation Barrier instruction - Vectorised implementation of XOR checksumming and CRC32 optimisations - Workaround for Cortex-A76 erratum #1165522 - Improved compatibility with Clang/LLD - Support for TX2 system PMUS for profiling the L3 cache and DMC - Reflect read-only permissions in the linear map by default - Ensure MMIO reads are ordered with subsequent calls to Xdelay() - Initial support for memory hotplug - Tweak the threshold when we invalidate the TLB by-ASID, so that mremap() performance is improved for ranges spanning multiple PMDs. - Minor refactoring and cleanups" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (125 commits) arm64: kaslr: print PHYS_OFFSET in dump_kernel_offset() arm64: sysreg: Use _BITUL() when defining register bits arm64: cpufeature: Rework ptr auth hwcaps using multi_entry_cap_matches arm64: cpufeature: Reduce number of pointer auth CPU caps from 6 to 4 arm64: docs: document pointer authentication arm64: ptr auth: Move per-thread keys from thread_info to thread_struct arm64: enable pointer authentication arm64: add prctl control for resetting ptrauth keys arm64: perf: strip PAC when unwinding userspace arm64: expose user PAC bit positions via ptrace arm64: add basic pointer authentication support arm64/cpufeature: detect pointer authentication arm64: Don't trap host pointer auth use to EL2 arm64/kvm: hide ptrauth from guests arm64/kvm: consistently handle host HCR_EL2 flags arm64: add pointer authentication register bits arm64: add comments about EC exception levels arm64: perf: Treat EXCLUDE_EL* bit definitions as unsigned arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field arm64: enable per-task stack canaries ...
266 lines
7.1 KiB
C
266 lines
7.1 KiB
C
/*
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* arch/arm64/kernel/ftrace.c
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*
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* Copyright (C) 2013 Linaro Limited
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* Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/ftrace.h>
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#include <linux/module.h>
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#include <linux/swab.h>
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/debug-monitors.h>
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#include <asm/ftrace.h>
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#include <asm/insn.h>
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#ifdef CONFIG_DYNAMIC_FTRACE
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/*
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* Replace a single instruction, which may be a branch or NOP.
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* If @validate == true, a replaced instruction is checked against 'old'.
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*/
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static int ftrace_modify_code(unsigned long pc, u32 old, u32 new,
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bool validate)
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{
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u32 replaced;
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/*
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* Note:
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* We are paranoid about modifying text, as if a bug were to happen, it
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* could cause us to read or write to someplace that could cause harm.
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* Carefully read and modify the code with aarch64_insn_*() which uses
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* probe_kernel_*(), and make sure what we read is what we expected it
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* to be before modifying it.
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*/
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if (validate) {
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if (aarch64_insn_read((void *)pc, &replaced))
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return -EFAULT;
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if (replaced != old)
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return -EINVAL;
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}
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if (aarch64_insn_patch_text_nosync((void *)pc, new))
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return -EPERM;
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return 0;
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}
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/*
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* Replace tracer function in ftrace_caller()
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*/
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int ftrace_update_ftrace_func(ftrace_func_t func)
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{
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unsigned long pc;
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u32 new;
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pc = (unsigned long)&ftrace_call;
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new = aarch64_insn_gen_branch_imm(pc, (unsigned long)func,
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AARCH64_INSN_BRANCH_LINK);
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return ftrace_modify_code(pc, 0, new, false);
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}
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/*
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* Turn on the call to ftrace_caller() in instrumented function
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*/
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int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
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{
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unsigned long pc = rec->ip;
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u32 old, new;
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long offset = (long)pc - (long)addr;
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if (offset < -SZ_128M || offset >= SZ_128M) {
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#ifdef CONFIG_ARM64_MODULE_PLTS
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struct plt_entry trampoline;
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struct module *mod;
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/*
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* On kernels that support module PLTs, the offset between the
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* branch instruction and its target may legally exceed the
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* range of an ordinary relative 'bl' opcode. In this case, we
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* need to branch via a trampoline in the module.
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*
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* NOTE: __module_text_address() must be called with preemption
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* disabled, but we can rely on ftrace_lock to ensure that 'mod'
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* retains its validity throughout the remainder of this code.
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*/
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preempt_disable();
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mod = __module_text_address(pc);
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preempt_enable();
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if (WARN_ON(!mod))
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return -EINVAL;
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/*
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* There is only one ftrace trampoline per module. For now,
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* this is not a problem since on arm64, all dynamic ftrace
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* invocations are routed via ftrace_caller(). This will need
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* to be revisited if support for multiple ftrace entry points
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* is added in the future, but for now, the pr_err() below
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* deals with a theoretical issue only.
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*/
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trampoline = get_plt_entry(addr, mod->arch.ftrace_trampoline);
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if (!plt_entries_equal(mod->arch.ftrace_trampoline,
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&trampoline)) {
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if (!plt_entries_equal(mod->arch.ftrace_trampoline,
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&(struct plt_entry){})) {
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pr_err("ftrace: far branches to multiple entry points unsupported inside a single module\n");
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return -EINVAL;
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}
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/* point the trampoline to our ftrace entry point */
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module_disable_ro(mod);
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*mod->arch.ftrace_trampoline = trampoline;
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module_enable_ro(mod, true);
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/* update trampoline before patching in the branch */
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smp_wmb();
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}
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addr = (unsigned long)(void *)mod->arch.ftrace_trampoline;
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#else /* CONFIG_ARM64_MODULE_PLTS */
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return -EINVAL;
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#endif /* CONFIG_ARM64_MODULE_PLTS */
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}
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old = aarch64_insn_gen_nop();
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new = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
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return ftrace_modify_code(pc, old, new, true);
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}
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/*
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* Turn off the call to ftrace_caller() in instrumented function
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*/
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int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
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unsigned long addr)
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{
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unsigned long pc = rec->ip;
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bool validate = true;
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u32 old = 0, new;
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long offset = (long)pc - (long)addr;
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if (offset < -SZ_128M || offset >= SZ_128M) {
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#ifdef CONFIG_ARM64_MODULE_PLTS
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u32 replaced;
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/*
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* 'mod' is only set at module load time, but if we end up
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* dealing with an out-of-range condition, we can assume it
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* is due to a module being loaded far away from the kernel.
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*/
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if (!mod) {
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preempt_disable();
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mod = __module_text_address(pc);
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preempt_enable();
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if (WARN_ON(!mod))
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return -EINVAL;
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}
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/*
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* The instruction we are about to patch may be a branch and
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* link instruction that was redirected via a PLT entry. In
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* this case, the normal validation will fail, but we can at
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* least check that we are dealing with a branch and link
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* instruction that points into the right module.
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*/
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if (aarch64_insn_read((void *)pc, &replaced))
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return -EFAULT;
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if (!aarch64_insn_is_bl(replaced) ||
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!within_module(pc + aarch64_get_branch_offset(replaced),
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mod))
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return -EINVAL;
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validate = false;
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#else /* CONFIG_ARM64_MODULE_PLTS */
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return -EINVAL;
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#endif /* CONFIG_ARM64_MODULE_PLTS */
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} else {
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old = aarch64_insn_gen_branch_imm(pc, addr,
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AARCH64_INSN_BRANCH_LINK);
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}
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new = aarch64_insn_gen_nop();
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return ftrace_modify_code(pc, old, new, validate);
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}
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void arch_ftrace_update_code(int command)
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{
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ftrace_modify_all_code(command);
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}
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int __init ftrace_dyn_arch_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_DYNAMIC_FTRACE */
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#ifdef CONFIG_FUNCTION_GRAPH_TRACER
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/*
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* function_graph tracer expects ftrace_return_to_handler() to be called
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* on the way back to parent. For this purpose, this function is called
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* in _mcount() or ftrace_caller() to replace return address (*parent) on
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* the call stack to return_to_handler.
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*
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* Note that @frame_pointer is used only for sanity check later.
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*/
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void prepare_ftrace_return(unsigned long self_addr, unsigned long *parent,
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unsigned long frame_pointer)
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{
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unsigned long return_hooker = (unsigned long)&return_to_handler;
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unsigned long old;
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if (unlikely(atomic_read(¤t->tracing_graph_pause)))
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return;
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/*
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* Note:
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* No protection against faulting at *parent, which may be seen
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* on other archs. It's unlikely on AArch64.
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*/
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old = *parent;
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if (!function_graph_enter(old, self_addr, frame_pointer, NULL))
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*parent = return_hooker;
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}
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#ifdef CONFIG_DYNAMIC_FTRACE
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/*
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* Turn on/off the call to ftrace_graph_caller() in ftrace_caller()
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* depending on @enable.
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*/
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static int ftrace_modify_graph_caller(bool enable)
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{
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unsigned long pc = (unsigned long)&ftrace_graph_call;
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u32 branch, nop;
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branch = aarch64_insn_gen_branch_imm(pc,
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(unsigned long)ftrace_graph_caller,
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AARCH64_INSN_BRANCH_NOLINK);
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nop = aarch64_insn_gen_nop();
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if (enable)
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return ftrace_modify_code(pc, nop, branch, true);
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else
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return ftrace_modify_code(pc, branch, nop, true);
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}
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int ftrace_enable_ftrace_graph_caller(void)
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{
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return ftrace_modify_graph_caller(true);
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}
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int ftrace_disable_ftrace_graph_caller(void)
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{
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return ftrace_modify_graph_caller(false);
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}
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#endif /* CONFIG_DYNAMIC_FTRACE */
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#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
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