Ville Syrjälä 56a12a5092 drm/i915: Include display_mmio_offset in sequencer index/data registers
SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-26 17:32:03 +01:00
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