64d4151658
Those macros are not doing the right thing with Sphinx 3, causing parse errors: ./Documentation/driver-api/fpga/fpga-mgr.rst:104: WARNING: Unparseable C cross-reference: 'fpga_manager->state' Invalid C declaration: Expected end of definition. [error at 12] fpga_manager->state ------------^ ./Documentation/driver-api/fpga/fpga-programming.rst:18: WARNING: Unparseable C cross-reference: 'fpga_region->info' Invalid C declaration: Expected end of definition. [error at 11] fpga_region->info -----------^ ./Documentation/driver-api/fpga/fpga-region.rst:62: WARNING: Unparseable C cross-reference: 'fpga_region->bridge_list' Invalid C declaration: Expected end of definition. [error at 11] fpga_region->bridge_list -----------^ ./Documentation/driver-api/fpga/fpga-region.rst:62: WARNING: Unparseable C cross-reference: 'fpga_region->get_bridges' Invalid C declaration: Expected end of definition. [error at 11] fpga_region->get_bridges -----------^ Replace them by :c:expr:, with does what's desired. Reviewed-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
128 lines
4.3 KiB
ReStructuredText
128 lines
4.3 KiB
ReStructuredText
FPGA Manager
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============
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Overview
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--------
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The FPGA manager core exports a set of functions for programming an FPGA with
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an image. The API is manufacturer agnostic. All manufacturer specifics are
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hidden away in a low level driver which registers a set of ops with the core.
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The FPGA image data itself is very manufacturer specific, but for our purposes
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it's just binary data. The FPGA manager core won't parse it.
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The FPGA image to be programmed can be in a scatter gather list, a single
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contiguous buffer, or a firmware file. Because allocating contiguous kernel
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memory for the buffer should be avoided, users are encouraged to use a scatter
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gather list instead if possible.
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The particulars for programming the image are presented in a structure (struct
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fpga_image_info). This struct contains parameters such as pointers to the
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FPGA image as well as image-specific particulars such as whether the image was
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built for full or partial reconfiguration.
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How to support a new FPGA device
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--------------------------------
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To add another FPGA manager, write a driver that implements a set of ops. The
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probe function calls fpga_mgr_register(), such as::
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static const struct fpga_manager_ops socfpga_fpga_ops = {
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.write_init = socfpga_fpga_ops_configure_init,
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.write = socfpga_fpga_ops_configure_write,
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.write_complete = socfpga_fpga_ops_configure_complete,
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.state = socfpga_fpga_ops_state,
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};
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static int socfpga_fpga_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct socfpga_fpga_priv *priv;
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struct fpga_manager *mgr;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/*
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* do ioremaps, get interrupts, etc. and save
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* them in priv
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*/
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mgr = devm_fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
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&socfpga_fpga_ops, priv);
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if (!mgr)
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return -ENOMEM;
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platform_set_drvdata(pdev, mgr);
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return fpga_mgr_register(mgr);
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}
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static int socfpga_fpga_remove(struct platform_device *pdev)
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{
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struct fpga_manager *mgr = platform_get_drvdata(pdev);
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fpga_mgr_unregister(mgr);
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return 0;
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}
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The ops will implement whatever device specific register writes are needed to
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do the programming sequence for this particular FPGA. These ops return 0 for
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success or negative error codes otherwise.
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The programming sequence is::
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1. .write_init
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2. .write or .write_sg (may be called once or multiple times)
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3. .write_complete
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The .write_init function will prepare the FPGA to receive the image data. The
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buffer passed into .write_init will be at most .initial_header_size bytes long;
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if the whole bitstream is not immediately available then the core code will
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buffer up at least this much before starting.
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The .write function writes a buffer to the FPGA. The buffer may be contain the
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whole FPGA image or may be a smaller chunk of an FPGA image. In the latter
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case, this function is called multiple times for successive chunks. This interface
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is suitable for drivers which use PIO.
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The .write_sg version behaves the same as .write except the input is a sg_table
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scatter list. This interface is suitable for drivers which use DMA.
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The .write_complete function is called after all the image has been written
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to put the FPGA into operating mode.
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The ops include a .state function which will determine the state the FPGA is in
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and return a code of type enum fpga_mgr_states. It doesn't result in a change
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in state.
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API for implementing a new FPGA Manager driver
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----------------------------------------------
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* ``fpga_mgr_states`` — Values for :c:expr:`fpga_manager->state`.
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* struct fpga_manager — the FPGA manager struct
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* struct fpga_manager_ops — Low level FPGA manager driver ops
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* devm_fpga_mgr_create() — Allocate and init a manager struct
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* fpga_mgr_register() — Register an FPGA manager
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* fpga_mgr_unregister() — Unregister an FPGA manager
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.. kernel-doc:: include/linux/fpga/fpga-mgr.h
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:functions: fpga_mgr_states
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.. kernel-doc:: include/linux/fpga/fpga-mgr.h
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:functions: fpga_manager
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.. kernel-doc:: include/linux/fpga/fpga-mgr.h
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:functions: fpga_manager_ops
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.. kernel-doc:: drivers/fpga/fpga-mgr.c
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:functions: devm_fpga_mgr_create
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.. kernel-doc:: drivers/fpga/fpga-mgr.c
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:functions: fpga_mgr_register
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.. kernel-doc:: drivers/fpga/fpga-mgr.c
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:functions: fpga_mgr_unregister
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