Swapnil Jakhade 0cfa43ab46 phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration ... Add register sequences for PCIe + SGMII PHY multilink configuration. This has been validated on TI J7 platforms. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2023-04-12 22:06:26 +05:30
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cdns-dphy-rx.c	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
cdns-dphy.c	phy: cadence: cdns-dphy: Convert to platform remove callback returning void	2023-03-20 18:14:56 +05:30
Kconfig	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
Makefile	phy: cadence: Add Cadence D-PHY Rx driver	2022-03-02 19:54:42 +05:30
phy-cadence-salvo.c	phy/cadence: Use of_device_get_match_data()	2022-02-25 13:58:12 +05:30
phy-cadence-sierra.c	phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration	2023-04-12 22:06:26 +05:30
phy-cadence-torrent.c	phy: cadence: phy-cadence-torrent: Convert to platform remove callback returning void	2023-03-20 18:14:56 +05:30