587f7031f3
When QCA988X cycle counter HW register wraps around it resets to 0x7fffffff instead of 0. All other cycle counter related registers are divided by 2 so they never wraparound themselves. QCA61X4 has a uniform CC and it wraparounds in a regular fashion though. Worst case wraparound time is approx 24 seconds (2**31 / 88MHz). Since scan channel visit times are max 5 seconds (offchannel case) it is guaranteed there's been at most 1 wraparound and it is possible to compute survey active time value. It is, however, impossible to determine the point at which Rx Clear Count has been divided by two so it is not reported upon wraparound. This fixes some occasional incorrect survey data on QCA988X as some channels (depending on how/when scan/offchannel requests were requested) would have approx 24 sec active time which wasn't actually the case. This should improve hostapd ACS a little bit. Reported-by: Srinivasa Duvvuri <sduvvuri@chromium.org> Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*
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* Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/types.h>
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#include "core.h"
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#include "hw.h"
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const struct ath10k_hw_regs qca988x_regs = {
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.rtc_state_cold_reset_mask = 0x00000400,
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.rtc_soc_base_address = 0x00004000,
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.rtc_wmac_base_address = 0x00005000,
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.soc_core_base_address = 0x00009000,
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.ce_wrapper_base_address = 0x00057000,
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.ce0_base_address = 0x00057400,
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.ce1_base_address = 0x00057800,
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.ce2_base_address = 0x00057c00,
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.ce3_base_address = 0x00058000,
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.ce4_base_address = 0x00058400,
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.ce5_base_address = 0x00058800,
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.ce6_base_address = 0x00058c00,
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.ce7_base_address = 0x00059000,
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00040000,
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.soc_chip_id_address = 0x00ec,
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.scratch_3_address = 0x0030,
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};
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const struct ath10k_hw_regs qca6174_regs = {
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.rtc_state_cold_reset_mask = 0x00002000,
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.rtc_soc_base_address = 0x00000800,
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.rtc_wmac_base_address = 0x00001000,
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.soc_core_base_address = 0x0003a000,
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.ce_wrapper_base_address = 0x00034000,
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.ce0_base_address = 0x00034400,
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.ce1_base_address = 0x00034800,
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.ce2_base_address = 0x00034c00,
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.ce3_base_address = 0x00035000,
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.ce4_base_address = 0x00035400,
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.ce5_base_address = 0x00035800,
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.ce6_base_address = 0x00035c00,
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.ce7_base_address = 0x00036000,
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.soc_reset_control_si0_rst_mask = 0x00000000,
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.soc_reset_control_ce_rst_mask = 0x00000001,
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.soc_chip_id_address = 0x000f0,
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.scratch_3_address = 0x0028,
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};
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
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{
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u32 cc_fix = 0;
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survey->filled |= SURVEY_INFO_TIME |
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SURVEY_INFO_TIME_BUSY;
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if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {
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cc_fix = 0x7fffffff;
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survey->filled &= ~SURVEY_INFO_TIME_BUSY;
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}
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cc -= cc_prev - cc_fix;
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rcc -= rcc_prev;
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survey->time = CCNT_TO_MSEC(cc);
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survey->time_busy = CCNT_TO_MSEC(rcc);
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}
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