e08efef8fe
Since the beginning the second clock ('special', 'sclk') was optional and
it is not available on some variants of Exynos SoCs (i.e. Exynos5420 with
v7 of MFC hardware).
However commit 1bce6fb3edf1 ("[media] s5p-mfc: Rework clock handling")
made handling of all specified clocks mandatory. This patch restores
original behavior of the driver and fixes its operation on
Exynos5420 SoCs.
Fixes: 1bce6fb3edf1 ("[media] s5p-mfc: Rework clock handling")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
120 lines
2.3 KiB
C
120 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* linux/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "s5p_mfc_common.h"
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#include "s5p_mfc_debug.h"
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#include "s5p_mfc_pm.h"
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static struct s5p_mfc_pm *pm;
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static struct s5p_mfc_dev *p_dev;
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static atomic_t clk_ref;
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int s5p_mfc_init_pm(struct s5p_mfc_dev *dev)
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{
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int i;
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pm = &dev->pm;
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p_dev = dev;
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pm->num_clocks = dev->variant->num_clocks;
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pm->clk_names = dev->variant->clk_names;
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pm->device = &dev->plat_dev->dev;
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pm->clock_gate = NULL;
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/* clock control */
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for (i = 0; i < pm->num_clocks; i++) {
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pm->clocks[i] = devm_clk_get(pm->device, pm->clk_names[i]);
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if (IS_ERR(pm->clocks[i])) {
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/* additional clocks are optional */
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if (i && PTR_ERR(pm->clocks[i]) == -ENOENT) {
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pm->clocks[i] = NULL;
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continue;
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}
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mfc_err("Failed to get clock: %s\n",
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pm->clk_names[i]);
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return PTR_ERR(pm->clocks[i]);
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}
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}
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if (dev->variant->use_clock_gating)
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pm->clock_gate = pm->clocks[0];
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pm_runtime_enable(pm->device);
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atomic_set(&clk_ref, 0);
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return 0;
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}
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void s5p_mfc_final_pm(struct s5p_mfc_dev *dev)
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{
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pm_runtime_disable(pm->device);
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}
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int s5p_mfc_clock_on(void)
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{
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atomic_inc(&clk_ref);
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mfc_debug(3, "+ %d\n", atomic_read(&clk_ref));
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return clk_enable(pm->clock_gate);
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}
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void s5p_mfc_clock_off(void)
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{
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atomic_dec(&clk_ref);
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mfc_debug(3, "- %d\n", atomic_read(&clk_ref));
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clk_disable(pm->clock_gate);
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}
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int s5p_mfc_power_on(void)
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{
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int i, ret = 0;
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ret = pm_runtime_get_sync(pm->device);
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if (ret < 0)
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return ret;
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/* clock control */
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for (i = 0; i < pm->num_clocks; i++) {
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ret = clk_prepare_enable(pm->clocks[i]);
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if (ret < 0) {
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mfc_err("clock prepare failed for clock: %s\n",
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pm->clk_names[i]);
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i++;
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goto err;
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}
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}
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/* prepare for software clock gating */
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clk_disable(pm->clock_gate);
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return 0;
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err:
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while (--i > 0)
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clk_disable_unprepare(pm->clocks[i]);
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pm_runtime_put(pm->device);
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return ret;
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}
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int s5p_mfc_power_off(void)
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{
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int i;
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/* finish software clock gating */
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clk_enable(pm->clock_gate);
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for (i = 0; i < pm->num_clocks; i++)
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clk_disable_unprepare(pm->clocks[i]);
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return pm_runtime_put_sync(pm->device);
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}
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