5876dd249e
Touching vram while the card is reclocking can lead to lockups. Unmap any pages that could be touched by the CPU and block any accesses to vram until the reclocking is complete. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
543 lines
16 KiB
C
543 lines
16 KiB
C
/*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Rafał Miłecki <zajec5@gmail.com>
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* Alex Deucher <alexdeucher@gmail.com>
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "avivod.h"
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#define RADEON_IDLE_LOOP_MS 100
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#define RADEON_RECLOCK_DELAY_MS 200
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#define RADEON_WAIT_VBLANK_TIMEOUT 200
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#define RADEON_WAIT_IDLE_TIMEOUT 200
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static void radeon_pm_idle_work_handler(struct work_struct *work);
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static int radeon_debugfs_pm_init(struct radeon_device *rdev);
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static void radeon_unmap_vram_bos(struct radeon_device *rdev)
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{
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struct radeon_bo *bo, *n;
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if (list_empty(&rdev->gem.objects))
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return;
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list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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ttm_bo_unmap_virtual(&bo->tbo);
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}
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if (rdev->gart.table.vram.robj)
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ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
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if (rdev->stollen_vga_memory)
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ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
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if (rdev->r600_blit.shader_obj)
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ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
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}
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static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
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{
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int i;
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mutex_lock(&rdev->cp.mutex);
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/* wait for GPU idle */
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rdev->pm.gui_idle = false;
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rdev->irq.gui_idle = true;
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radeon_irq_set(rdev);
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wait_event_interruptible_timeout(
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rdev->irq.idle_queue, rdev->pm.gui_idle,
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msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
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rdev->irq.gui_idle = false;
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radeon_irq_set(rdev);
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mutex_lock(&rdev->vram_mutex);
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radeon_unmap_vram_bos(rdev);
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if (!static_switch) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.active_crtcs & (1 << i)) {
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rdev->pm.req_vblank |= (1 << i);
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drm_vblank_get(rdev->ddev, i);
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}
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}
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}
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radeon_set_power_state(rdev, static_switch);
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if (!static_switch) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.req_vblank & (1 << i)) {
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rdev->pm.req_vblank &= ~(1 << i);
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drm_vblank_put(rdev->ddev, i);
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}
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}
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}
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mutex_unlock(&rdev->vram_mutex);
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/* update display watermarks based on new power state */
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radeon_update_bandwidth_info(rdev);
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if (rdev->pm.active_crtc_count)
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radeon_bandwidth_update(rdev);
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rdev->pm.planned_action = PM_ACTION_NONE;
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mutex_unlock(&rdev->cp.mutex);
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}
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static ssize_t radeon_get_power_state_static(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
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rdev->pm.current_clock_mode_index);
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}
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static ssize_t radeon_set_power_state_static(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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int ps, cm;
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if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
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DRM_ERROR("Invalid power state!\n");
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return count;
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}
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mutex_lock(&rdev->pm.mutex);
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if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
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(cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
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if ((rdev->pm.active_crtc_count > 1) &&
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(rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
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DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
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} else {
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/* disable dynpm */
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rdev->pm.state = PM_STATE_DISABLED;
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rdev->pm.planned_action = PM_ACTION_NONE;
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rdev->pm.requested_power_state_index = ps;
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rdev->pm.requested_clock_mode_index = cm;
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radeon_pm_set_clocks(rdev, true);
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}
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} else
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DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
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mutex_unlock(&rdev->pm.mutex);
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return count;
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}
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static ssize_t radeon_get_dynpm(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
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}
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static ssize_t radeon_set_dynpm(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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int tmp = simple_strtoul(buf, NULL, 10);
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if (tmp == 0) {
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/* update power mode info */
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radeon_pm_compute_clocks(rdev);
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/* disable dynpm */
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.state = PM_STATE_DISABLED;
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rdev->pm.planned_action = PM_ACTION_NONE;
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mutex_unlock(&rdev->pm.mutex);
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DRM_INFO("radeon: dynamic power management disabled\n");
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} else if (tmp == 1) {
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if (rdev->pm.num_power_states > 1) {
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/* enable dynpm */
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.state = PM_STATE_PAUSED;
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rdev->pm.planned_action = PM_ACTION_DEFAULT;
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radeon_get_power_state(rdev, rdev->pm.planned_action);
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mutex_unlock(&rdev->pm.mutex);
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/* update power mode info */
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radeon_pm_compute_clocks(rdev);
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DRM_INFO("radeon: dynamic power management enabled\n");
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} else
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DRM_ERROR("dynpm not valid on this system\n");
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} else
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DRM_ERROR("Invalid setting: %d\n", tmp);
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return count;
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}
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static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
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static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
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static const char *pm_state_names[4] = {
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"PM_STATE_DISABLED",
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"PM_STATE_MINIMUM",
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"PM_STATE_PAUSED",
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"PM_STATE_ACTIVE"
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};
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static const char *pm_state_types[5] = {
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"",
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"Powersave",
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"Battery",
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"Balanced",
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"Performance",
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};
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static void radeon_print_power_mode_info(struct radeon_device *rdev)
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{
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int i, j;
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bool is_default;
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DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
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for (i = 0; i < rdev->pm.num_power_states; i++) {
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if (rdev->pm.default_power_state_index == i)
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is_default = true;
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else
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is_default = false;
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DRM_INFO("State %d %s %s\n", i,
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pm_state_types[rdev->pm.power_state[i].type],
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is_default ? "(default)" : "");
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if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
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DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
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if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
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DRM_INFO("\tSingle display only\n");
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DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
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for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
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if (rdev->flags & RADEON_IS_IGP)
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DRM_INFO("\t\t%d engine: %d\n",
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j,
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rdev->pm.power_state[i].clock_info[j].sclk * 10);
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else
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DRM_INFO("\t\t%d engine/memory: %d/%d\n",
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j,
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rdev->pm.power_state[i].clock_info[j].sclk * 10,
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rdev->pm.power_state[i].clock_info[j].mclk * 10);
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}
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}
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}
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void radeon_sync_with_vblank(struct radeon_device *rdev)
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{
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if (rdev->pm.active_crtcs) {
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rdev->pm.vblank_sync = false;
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wait_event_timeout(
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rdev->irq.vblank_queue, rdev->pm.vblank_sync,
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msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
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}
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}
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int radeon_pm_init(struct radeon_device *rdev)
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{
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rdev->pm.state = PM_STATE_DISABLED;
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rdev->pm.planned_action = PM_ACTION_NONE;
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rdev->pm.can_upclock = true;
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rdev->pm.can_downclock = true;
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if (rdev->bios) {
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if (rdev->is_atom_bios)
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radeon_atombios_get_power_modes(rdev);
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else
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radeon_combios_get_power_modes(rdev);
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radeon_print_power_mode_info(rdev);
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}
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if (radeon_debugfs_pm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for PM!\n");
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}
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/* where's the best place to put this? */
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device_create_file(rdev->dev, &dev_attr_power_state);
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device_create_file(rdev->dev, &dev_attr_dynpm);
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INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
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if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
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rdev->pm.state = PM_STATE_PAUSED;
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DRM_INFO("radeon: dynamic power management enabled\n");
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}
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DRM_INFO("radeon: power management initialized\n");
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return 0;
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}
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void radeon_pm_fini(struct radeon_device *rdev)
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{
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if (rdev->pm.state != PM_STATE_DISABLED) {
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/* cancel work */
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cancel_delayed_work_sync(&rdev->pm.idle_work);
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/* reset default clocks */
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rdev->pm.state = PM_STATE_DISABLED;
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rdev->pm.planned_action = PM_ACTION_DEFAULT;
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radeon_pm_set_clocks(rdev, false);
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} else if ((rdev->pm.current_power_state_index !=
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rdev->pm.default_power_state_index) ||
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(rdev->pm.current_clock_mode_index != 0)) {
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rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
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rdev->pm.requested_clock_mode_index = 0;
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mutex_lock(&rdev->pm.mutex);
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radeon_pm_set_clocks(rdev, true);
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mutex_unlock(&rdev->pm.mutex);
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}
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device_remove_file(rdev->dev, &dev_attr_power_state);
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device_remove_file(rdev->dev, &dev_attr_dynpm);
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if (rdev->pm.i2c_bus)
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radeon_i2c_destroy(rdev->pm.i2c_bus);
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}
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void radeon_pm_compute_clocks(struct radeon_device *rdev)
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{
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struct drm_device *ddev = rdev->ddev;
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struct drm_crtc *crtc;
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struct radeon_crtc *radeon_crtc;
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if (rdev->pm.state == PM_STATE_DISABLED)
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return;
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.active_crtcs = 0;
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rdev->pm.active_crtc_count = 0;
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list_for_each_entry(crtc,
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&ddev->mode_config.crtc_list, head) {
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radeon_crtc = to_radeon_crtc(crtc);
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if (radeon_crtc->enabled) {
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rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
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rdev->pm.active_crtc_count++;
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}
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}
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if (rdev->pm.active_crtc_count > 1) {
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if (rdev->pm.state == PM_STATE_ACTIVE) {
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cancel_delayed_work(&rdev->pm.idle_work);
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rdev->pm.state = PM_STATE_PAUSED;
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rdev->pm.planned_action = PM_ACTION_UPCLOCK;
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radeon_pm_set_clocks(rdev, false);
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DRM_DEBUG("radeon: dynamic power management deactivated\n");
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}
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} else if (rdev->pm.active_crtc_count == 1) {
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/* TODO: Increase clocks if needed for current mode */
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if (rdev->pm.state == PM_STATE_MINIMUM) {
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rdev->pm.state = PM_STATE_ACTIVE;
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rdev->pm.planned_action = PM_ACTION_UPCLOCK;
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radeon_pm_set_clocks(rdev, false);
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queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
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msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
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} else if (rdev->pm.state == PM_STATE_PAUSED) {
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rdev->pm.state = PM_STATE_ACTIVE;
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queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
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msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
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DRM_DEBUG("radeon: dynamic power management activated\n");
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}
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} else { /* count == 0 */
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if (rdev->pm.state != PM_STATE_MINIMUM) {
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cancel_delayed_work(&rdev->pm.idle_work);
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rdev->pm.state = PM_STATE_MINIMUM;
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rdev->pm.planned_action = PM_ACTION_MINIMUM;
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radeon_pm_set_clocks(rdev, false);
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}
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}
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mutex_unlock(&rdev->pm.mutex);
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}
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bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
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{
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u32 stat_crtc = 0;
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bool in_vbl = true;
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if (ASIC_IS_DCE4(rdev)) {
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if (rdev->pm.active_crtcs & (1 << 0)) {
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stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 1)) {
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stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 2)) {
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stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 3)) {
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stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 4)) {
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stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 5)) {
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stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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} else if (ASIC_IS_AVIVO(rdev)) {
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if (rdev->pm.active_crtcs & (1 << 0)) {
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stat_crtc = RREG32(D1CRTC_STATUS);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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if (rdev->pm.active_crtcs & (1 << 1)) {
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stat_crtc = RREG32(D2CRTC_STATUS);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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} else {
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if (rdev->pm.active_crtcs & (1 << 0)) {
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stat_crtc = RREG32(RADEON_CRTC_STATUS);
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if (!(stat_crtc & 1))
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in_vbl = false;
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}
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|
if (rdev->pm.active_crtcs & (1 << 1)) {
|
|
stat_crtc = RREG32(RADEON_CRTC2_STATUS);
|
|
if (!(stat_crtc & 1))
|
|
in_vbl = false;
|
|
}
|
|
}
|
|
if (in_vbl == false)
|
|
DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
|
|
finish ? "exit" : "entry");
|
|
return in_vbl;
|
|
}
|
|
|
|
static void radeon_pm_idle_work_handler(struct work_struct *work)
|
|
{
|
|
struct radeon_device *rdev;
|
|
rdev = container_of(work, struct radeon_device,
|
|
pm.idle_work.work);
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->pm.state == PM_STATE_ACTIVE) {
|
|
unsigned long irq_flags;
|
|
int not_processed = 0;
|
|
|
|
read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
|
|
if (!list_empty(&rdev->fence_drv.emited)) {
|
|
struct list_head *ptr;
|
|
list_for_each(ptr, &rdev->fence_drv.emited) {
|
|
/* count up to 3, that's enought info */
|
|
if (++not_processed >= 3)
|
|
break;
|
|
}
|
|
}
|
|
read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
|
|
|
|
if (not_processed >= 3) { /* should upclock */
|
|
if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
|
|
rdev->pm.planned_action = PM_ACTION_NONE;
|
|
} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
|
|
rdev->pm.can_upclock) {
|
|
rdev->pm.planned_action =
|
|
PM_ACTION_UPCLOCK;
|
|
rdev->pm.action_timeout = jiffies +
|
|
msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
|
|
}
|
|
} else if (not_processed == 0) { /* should downclock */
|
|
if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
|
|
rdev->pm.planned_action = PM_ACTION_NONE;
|
|
} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
|
|
rdev->pm.can_downclock) {
|
|
rdev->pm.planned_action =
|
|
PM_ACTION_DOWNCLOCK;
|
|
rdev->pm.action_timeout = jiffies +
|
|
msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
|
|
}
|
|
}
|
|
|
|
if (rdev->pm.planned_action != PM_ACTION_NONE &&
|
|
jiffies > rdev->pm.action_timeout) {
|
|
radeon_pm_set_clocks(rdev, false);
|
|
}
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
|
|
msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
}
|
|
|
|
/*
|
|
* Debugfs info
|
|
*/
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
|
|
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
|
|
seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
|
|
seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
|
|
if (rdev->asic->get_memory_clock)
|
|
seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
|
|
if (rdev->asic->get_pcie_lanes)
|
|
seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list radeon_pm_info_list[] = {
|
|
{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
|
|
};
|
|
#endif
|
|
|
|
static int radeon_debugfs_pm_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|