a32b344e6f
New drivers: - Last merge window we created a driver for the Ralink RT2880. We are now moving the Ralink SoC pin control drivers out of the MIPS architecture code and into the pin control subsystem. This concerns RT288X, MT7620, RT305X, RT3883 and MT7621. - Qualcomm SM6125 SoC pin control driver. - Qualcomm spmi-gpio support for PM7325. - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string) - Mediatek MT8365 SoC pin controller. - New device HID for the AMD GPIO controller. Improvements: - Pin bias config support for a slew of Renesas pin controllers. - Incremental improvements and non-urgent bug fixes to the Renesas SoC drivers. - Implement irq_set_wake on the AMD pin controller so we can wake up from external pin events. Misc: - Devicetree bindings for the Apple M1 pin controller, we will probably see a proper driver for this soon as well. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmDeTu0ACgkQQRCzN7AZ XXO2Yg/+LHbqYX8V+Ig1ZcY4p5bfbGyyC6QG6g3d/kzzCmsjHFgmDFQoZ+LoRx+p FRUSvmiR0VERMZCEepHsZgzns6ezzJfBt4Cu/388d4iYZppaETpQV47TzqY3eP7Q 4Shu2wIKwd7C3vNrCifub0JOYAAEsqdlHd75g0bqhal9hgH/MgYQSq9F22/TKAFl hteFwyw5L4OwKIDUpqDOIcG8thhHYWrQy77/Pp82/TVnmO9gamt863dKBjIg6iF9 c+pmIWI8K2mBhNO+epGG4VSroUudIBwKV88nwUjKSe+pu0VAU7lit/V0Uh1IhG0s FUHHGDeF62Ncn4SOYetlnSlKbQkhJaBDV2sDgQ3xzqvs1P3WEHRWqYIh1egq5iW6 /KtpSlRLQ/aO+k0iN66pErpAfsGNFAxkqlCSypyJG7ROnb2rADzZ0ftEKQb8RzZb nypPupOO5/bFfQHbQtFORDaNu9MUTR5PR04eTPMoApG0nv7zY+kcJ6iJuKE9spLb ahoxLstfQ/fKK27yms72E6PqwanuUEzcQv7gjhuHmFEjNrW1ARUqoa5hpdAzhZOX 20P8SZWkSeUZnqB26YQq+1U9p6wV0064Vp+jYY/wzQpV40dgX9oumiRkxCWCzpjt 6mw6x9txlrEEu+2WadW8yZd4ewKvWFLEGI+C/83pnI5NF1Dp0Go= =Ajcr -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.14 kernel. Not so much going on. No core changes, just drivers. The most interesting would be that MIPS Ralink is migrating to pin control and we have some bindings but not yet code for the Apple M1 pin controller. New drivers: - Last merge window we created a driver for the Ralink RT2880. We are now moving the Ralink SoC pin control drivers out of the MIPS architecture code and into the pin control subsystem. This concerns RT288X, MT7620, RT305X, RT3883 and MT7621. - Qualcomm SM6125 SoC pin control driver. - Qualcomm spmi-gpio support for PM7325. - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string) - Mediatek MT8365 SoC pin controller. - New device HID for the AMD GPIO controller. Improvements: - Pin bias config support for a slew of Renesas pin controllers. - Incremental improvements and non-urgent bug fixes to the Renesas SoC drivers. - Implement irq_set_wake on the AMD pin controller so we can wake up from external pin events. Misc: - Devicetree bindings for the Apple M1 pin controller, we will probably see a proper driver for this soon as well" * tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits) pinctrl: ralink: rt305x: add missing include pinctrl: stm32: check for IRQ MUX validity during alloc() pinctrl: zynqmp: some code cleanups drivers: qcom: pinctrl: Add pinctrl driver for sm6125 dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios pinctrl: mcp23s08: Add optional reset GPIO pinctrl: mediatek: fix mode encoding pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() pinctrl: bcm: Constify static pinmux_ops pinctrl: bcm: Constify static pinctrl_ops pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file pinctrl: ralink: move ralink architecture pinmux header into the driver pinctrl: single: config: enable the pin's input pinctrl: mtk: Fix mt8365 Kconfig dependency pinctrl: mcp23s08: fix race condition in irq handler ...
350 lines
8.2 KiB
C
350 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
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#include "pinmux.h"
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#include "../core.h"
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#include "../pinctrl-utils.h"
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#define SYSC_REG_GPIO_MODE 0x60
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#define SYSC_REG_GPIO_MODE2 0x64
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struct rt2880_priv {
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struct device *dev;
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struct pinctrl_pin_desc *pads;
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struct pinctrl_desc *desc;
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struct rt2880_pmx_func **func;
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int func_count;
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struct rt2880_pmx_group *groups;
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const char **group_names;
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int group_count;
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u8 *gpio;
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int max_pins;
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};
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static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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return p->group_count;
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}
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static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
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unsigned int group)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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return (group >= p->group_count) ? NULL : p->group_names[group];
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}
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static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
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unsigned int group,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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if (group >= p->group_count)
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return -EINVAL;
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*pins = p->groups[group].func[0].pins;
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*num_pins = p->groups[group].func[0].pin_count;
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return 0;
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}
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static const struct pinctrl_ops rt2880_pctrl_ops = {
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.get_groups_count = rt2880_get_group_count,
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.get_group_name = rt2880_get_group_name,
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.get_group_pins = rt2880_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinconf_generic_dt_free_map,
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};
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static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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return p->func_count;
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}
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static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
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unsigned int func)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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return p->func[func]->name;
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}
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static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
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unsigned int func,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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if (p->func[func]->group_count == 1)
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*groups = &p->group_names[p->func[func]->groups[0]];
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else
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*groups = p->group_names;
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*num_groups = p->func[func]->group_count;
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return 0;
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}
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static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
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unsigned int func, unsigned int group)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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u32 mode = 0;
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u32 reg = SYSC_REG_GPIO_MODE;
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int i;
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int shift;
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/* dont allow double use */
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if (p->groups[group].enabled) {
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dev_err(p->dev, "%s is already enabled\n",
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p->groups[group].name);
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return 0;
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}
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p->groups[group].enabled = 1;
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p->func[func]->enabled = 1;
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shift = p->groups[group].shift;
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if (shift >= 32) {
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shift -= 32;
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reg = SYSC_REG_GPIO_MODE2;
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}
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mode = rt_sysc_r32(reg);
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mode &= ~(p->groups[group].mask << shift);
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/* mark the pins as gpio */
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for (i = 0; i < p->groups[group].func[0].pin_count; i++)
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p->gpio[p->groups[group].func[0].pins[i]] = 1;
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/* function 0 is gpio and needs special handling */
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if (func == 0) {
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mode |= p->groups[group].gpio << shift;
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} else {
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for (i = 0; i < p->func[func]->pin_count; i++)
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p->gpio[p->func[func]->pins[i]] = 0;
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mode |= p->func[func]->value << shift;
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}
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rt_sysc_w32(mode, reg);
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return 0;
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}
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static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin)
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{
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struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
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if (!p->gpio[pin]) {
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dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
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return -EINVAL;
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}
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return 0;
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}
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static const struct pinmux_ops rt2880_pmx_group_ops = {
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.get_functions_count = rt2880_pmx_func_count,
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.get_function_name = rt2880_pmx_func_name,
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.get_function_groups = rt2880_pmx_group_get_groups,
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.set_mux = rt2880_pmx_group_enable,
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.gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
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};
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static struct pinctrl_desc rt2880_pctrl_desc = {
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.owner = THIS_MODULE,
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.name = "rt2880-pinmux",
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.pctlops = &rt2880_pctrl_ops,
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.pmxops = &rt2880_pmx_group_ops,
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};
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static struct rt2880_pmx_func gpio_func = {
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.name = "gpio",
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};
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static int rt2880_pinmux_index(struct rt2880_priv *p)
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{
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struct rt2880_pmx_group *mux = p->groups;
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int i, j, c = 0;
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/* count the mux functions */
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while (mux->name) {
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p->group_count++;
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mux++;
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}
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/* allocate the group names array needed by the gpio function */
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p->group_names = devm_kcalloc(p->dev, p->group_count,
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sizeof(char *), GFP_KERNEL);
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if (!p->group_names)
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return -ENOMEM;
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for (i = 0; i < p->group_count; i++) {
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p->group_names[i] = p->groups[i].name;
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p->func_count += p->groups[i].func_count;
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}
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/* we have a dummy function[0] for gpio */
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p->func_count++;
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/* allocate our function and group mapping index buffers */
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p->func = devm_kcalloc(p->dev, p->func_count,
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sizeof(*p->func), GFP_KERNEL);
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gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int),
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GFP_KERNEL);
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if (!p->func || !gpio_func.groups)
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return -ENOMEM;
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/* add a backpointer to the function so it knows its group */
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gpio_func.group_count = p->group_count;
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for (i = 0; i < gpio_func.group_count; i++)
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gpio_func.groups[i] = i;
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p->func[c] = &gpio_func;
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c++;
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/* add remaining functions */
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for (i = 0; i < p->group_count; i++) {
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for (j = 0; j < p->groups[i].func_count; j++) {
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p->func[c] = &p->groups[i].func[j];
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p->func[c]->groups = devm_kzalloc(p->dev, sizeof(int),
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GFP_KERNEL);
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if (!p->func[c]->groups)
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return -ENOMEM;
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p->func[c]->groups[0] = i;
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p->func[c]->group_count = 1;
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c++;
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}
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}
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return 0;
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}
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static int rt2880_pinmux_pins(struct rt2880_priv *p)
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{
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int i, j;
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/*
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* loop over the functions and initialize the pins array.
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* also work out the highest pin used.
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*/
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for (i = 0; i < p->func_count; i++) {
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int pin;
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if (!p->func[i]->pin_count)
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continue;
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p->func[i]->pins = devm_kcalloc(p->dev,
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p->func[i]->pin_count,
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sizeof(int),
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GFP_KERNEL);
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for (j = 0; j < p->func[i]->pin_count; j++)
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p->func[i]->pins[j] = p->func[i]->pin_first + j;
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pin = p->func[i]->pin_first + p->func[i]->pin_count;
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if (pin > p->max_pins)
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p->max_pins = pin;
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}
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/* the buffer that tells us which pins are gpio */
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p->gpio = devm_kcalloc(p->dev, p->max_pins, sizeof(u8), GFP_KERNEL);
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/* the pads needed to tell pinctrl about our pins */
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p->pads = devm_kcalloc(p->dev, p->max_pins,
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sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
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if (!p->pads || !p->gpio)
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return -ENOMEM;
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memset(p->gpio, 1, sizeof(u8) * p->max_pins);
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for (i = 0; i < p->func_count; i++) {
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if (!p->func[i]->pin_count)
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continue;
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for (j = 0; j < p->func[i]->pin_count; j++)
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p->gpio[p->func[i]->pins[j]] = 0;
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}
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/* pin 0 is always a gpio */
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p->gpio[0] = 1;
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/* set the pads */
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for (i = 0; i < p->max_pins; i++) {
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/* strlen("ioXY") + 1 = 5 */
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char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
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if (!name)
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return -ENOMEM;
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snprintf(name, 5, "io%d", i);
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p->pads[i].number = i;
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p->pads[i].name = name;
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}
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p->desc->pins = p->pads;
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p->desc->npins = p->max_pins;
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return 0;
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}
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int rt2880_pinmux_init(struct platform_device *pdev,
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struct rt2880_pmx_group *data)
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{
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struct rt2880_priv *p;
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struct pinctrl_dev *dev;
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int err;
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if (!data)
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return -ENOTSUPP;
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/* setup the private data */
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p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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p->dev = &pdev->dev;
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p->desc = &rt2880_pctrl_desc;
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p->groups = data;
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platform_set_drvdata(pdev, p);
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/* init the device */
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err = rt2880_pinmux_index(p);
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if (err) {
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dev_err(&pdev->dev, "failed to load index\n");
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return err;
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}
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err = rt2880_pinmux_pins(p);
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if (err) {
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dev_err(&pdev->dev, "failed to load pins\n");
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return err;
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}
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dev = pinctrl_register(p->desc, &pdev->dev, p);
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return PTR_ERR_OR_ZERO(dev);
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}
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