Geert Uytterhoeven 5915838b7a clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-25 08:55:56 +02:00
..
2018-07-06 11:12:20 -07:00
2018-08-23 13:44:43 -07:00
2017-11-03 09:02:30 -07:00
2018-07-09 13:49:31 +02:00
2017-11-01 23:25:43 -07:00
2018-07-06 13:52:57 -07:00
2018-08-23 13:52:46 -07:00
2018-03-16 15:53:30 -07:00
2018-06-12 16:19:22 -07:00
2018-06-12 16:19:22 -07:00
2016-03-02 17:48:26 -08:00
2018-07-06 13:44:06 -07:00
2016-10-23 10:18:45 -07:00
2017-11-01 23:25:51 -07:00
2017-11-01 23:25:51 -07:00
2018-07-06 13:44:06 -07:00