Dan Williams 5a84711fd7 cxl/pci: Fix irq oneshot expectations ... The IRQ core expects that users of the default hardirq handler specify IRQF_ONESHOT to keep interrupts disabled until the threaded handler runs. That meets the CXL driver's expectations since it is an edge triggered MSI and this flag would have been passed by default using pci_request_irq() instead of devm_request_threaded_irq(). Fixes: a49aa8141b ("cxl/mem: Wire up event interrupts") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Cc: Davidlohr Bueso <dave@stgolabs.net> Cc: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-01-30 15:39:26 -08:00
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core	cxl/pci: Set the device timestamp	2023-01-30 11:30:51 -08:00
acpi.c	cxl: update names for interleave ways conversion macros	2022-12-05 18:17:16 -08:00
cxl.h	cxl/mem: Wire up event interrupts	2023-01-26 16:51:07 -08:00
cxlmem.h	cxl/pci: Set the device timestamp	2023-01-30 11:30:51 -08:00
cxlpci.h	cxl/mem: Wire up event interrupts	2023-01-26 16:51:07 -08:00
Kconfig	cxl/region: Manage CPU caches relative to DPA invalidation events	2022-12-03 00:03:57 -08:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
mem.c	cxl/port: Add RCD endpoint port enumeration	2022-12-05 10:32:26 -08:00
pci.c	cxl/pci: Fix irq oneshot expectations	2023-01-30 15:39:26 -08:00
pmem.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
security.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00