5aa85c9fc4
The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source.
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/*
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* Copyright (C) 2001, 2002, MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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* Copyright (c) 2003 Maciej W. Rozycki
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*
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* include/asm-mips/time.h
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* header file for the new style time.c file and time services.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_TIME_H
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#define _ASM_TIME_H
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#include <linux/rtc.h>
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#include <linux/spinlock.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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extern spinlock_t rtc_lock;
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/*
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* RTC ops. By default, they point to weak no-op RTC functions.
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* rtc_mips_set_time - reverse the above translation and set time to RTC.
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* rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need
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* to be set. Used by RTC sync-up.
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*/
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extern int rtc_mips_set_time(unsigned long);
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extern int rtc_mips_set_mmss(unsigned long);
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/*
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* Timer interrupt functions.
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* mips_timer_state is needed for high precision timer calibration.
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*/
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extern int (*mips_timer_state)(void);
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/*
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* board specific routines required by time_init().
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*/
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extern void plat_time_init(void);
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/*
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* mips_hpt_frequency - must be set if you intend to use an R4k-compatible
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* counter as a timer interrupt source; otherwise it can be set up
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* automagically with an aid of mips_timer_state.
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*/
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extern unsigned int mips_hpt_frequency;
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/*
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* The performance counter IRQ on MIPS is a close relative to the timer IRQ
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* so it lives here.
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*/
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extern int (*perf_irq)(void);
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/*
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* Initialize the calling CPU's compare interrupt as clockevent device
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*/
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#ifdef CONFIG_CEVT_R4K
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extern int mips_clockevent_init(void);
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extern unsigned int __weak get_c0_compare_int(void);
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#else
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static inline int mips_clockevent_init(void)
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{
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return -ENXIO;
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}
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#endif
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extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
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extern void clockevent_set_clock(struct clock_event_device *cd,
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unsigned int clock);
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#endif /* _ASM_TIME_H */
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