e34645f458
Add SMP support for i.MX7D, including CPU hotplug support, for systems where TFA is not present. The motivation for bringing up the second i.MX7D core inside the kernel is that legacy vendor bootloaders usually do not implement PSCI support. This is a significant blocker for systems in the field that are running old bootloader versions to upgrade to a modern mainline kernel version, as only one CPU of the i.MX7D would be brought up. Bring up the second i.MX7D core inside the kernel to make the migration path to mainline kernel easier for the existing iMX7D users. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com> # Fix merge conflicts Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> # heavy cleanup Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
89 lines
1.9 KiB
C
89 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
|
*/
|
|
#include <linux/irqchip.h>
|
|
#include <linux/mfd/syscon.h>
|
|
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
|
|
#include <linux/of_platform.h>
|
|
#include <linux/phy.h>
|
|
#include <linux/regmap.h>
|
|
|
|
#include <asm/mach/arch.h>
|
|
#include <asm/mach/map.h>
|
|
|
|
#include "common.h"
|
|
|
|
static int bcm54220_phy_fixup(struct phy_device *dev)
|
|
{
|
|
/* enable RXC skew select RGMII copper mode */
|
|
phy_write(dev, 0x1e, 0x21);
|
|
phy_write(dev, 0x1f, 0x7ea8);
|
|
phy_write(dev, 0x1e, 0x2f);
|
|
phy_write(dev, 0x1f, 0x71b7);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define PHY_ID_BCM54220 0x600d8589
|
|
|
|
static void __init imx7d_enet_phy_init(void)
|
|
{
|
|
if (IS_BUILTIN(CONFIG_PHYLIB)) {
|
|
phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
|
|
bcm54220_phy_fixup);
|
|
}
|
|
}
|
|
|
|
static void __init imx7d_enet_clk_sel(void)
|
|
{
|
|
struct regmap *gpr;
|
|
|
|
gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
|
|
if (!IS_ERR(gpr)) {
|
|
regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
|
|
regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
|
|
} else {
|
|
pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
|
|
}
|
|
}
|
|
|
|
static inline void imx7d_enet_init(void)
|
|
{
|
|
imx7d_enet_phy_init();
|
|
imx7d_enet_clk_sel();
|
|
}
|
|
|
|
static void __init imx7d_init_machine(void)
|
|
{
|
|
imx_anatop_init();
|
|
imx7d_enet_init();
|
|
}
|
|
|
|
static void __init imx7d_init_late(void)
|
|
{
|
|
if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
|
|
platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
|
|
}
|
|
|
|
static void __init imx7d_init_irq(void)
|
|
{
|
|
imx_init_revision_from_anatop();
|
|
imx7_src_init();
|
|
irqchip_init();
|
|
}
|
|
|
|
static const char *const imx7d_dt_compat[] __initconst = {
|
|
"fsl,imx7d",
|
|
"fsl,imx7s",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
|
|
.smp = smp_ops(imx7_smp_ops),
|
|
.init_irq = imx7d_init_irq,
|
|
.init_machine = imx7d_init_machine,
|
|
.init_late = imx7d_init_late,
|
|
.dt_compat = imx7d_dt_compat,
|
|
MACHINE_END
|